Jagdish Sabde

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Partial memory die with inter-plane re-mapping
- Patent number 10,776,277
- Issue date Sep 15, 2020
- SanDisk Technologies LLC
- Daniel Linnen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parity relocation for reducing temperature throttling
- Patent number 10,564,861
- Issue date Feb 18, 2020
- Western Digital Technologies, Inc.
- Daniel Joseph Linnen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partial memory die
- Patent number 10,290,354
- Issue date May 14, 2019
- SanDisk Technologies LLC
- Daniel Linnen
- G11 - INFORMATION STORAGE
Information Patent Grant
High-speed data path testing techniques for non-volatile memory
- Patent number 10,242,750
- Issue date Mar 26, 2019
- SanDisk Technologies LLC
- Daniel Linnen
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for determining local interconnect defects
- Patent number 10,032,524
- Issue date Jul 24, 2018
- SanDisk Technologies LLC
- Jagdish Sabde
- G11 - INFORMATION STORAGE
Information Patent Grant
NAND structure with tier select gate transistors
- Patent number 9,953,717
- Issue date Apr 24, 2018
- SanDisk Technologies LLC
- Jagdish Sabde
- G11 - INFORMATION STORAGE
Information Patent Grant
Erase stress and delta erase loop count methods for various fail mo...
- Patent number 9,934,872
- Issue date Apr 3, 2018
- SanDisk Technologies LLC
- Sagar Magia
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-tier memory stack structure containing non-overlapping suppor...
- Patent number 9,881,929
- Issue date Jan 30, 2018
- SanDisk Technologies LLC
- Pradhyumna Ravikirthi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stress patterns to detect shorts in three dimensional non-volatile...
- Patent number 9,830,998
- Issue date Nov 28, 2017
- SanDisk Technologies LLC
- Jayavel Pachamuthu
- G11 - INFORMATION STORAGE
Information Patent Grant
Determination of word line to word line shorts between adjacent blocks
- Patent number 9,653,175
- Issue date May 16, 2017
- SanDisk Technologies LLC
- Jagdish Sabde
- G11 - INFORMATION STORAGE
Information Patent Grant
Current based detection and recording of memory hole-interconnect s...
- Patent number 9,564,219
- Issue date Feb 7, 2017
- SanDisk Technologies LLC
- Sagar Magia
- G11 - INFORMATION STORAGE
Information Patent Grant
Word line look ahead read for word line to word line short detection
- Patent number 9,548,129
- Issue date Jan 17, 2017
- SanDisk Technologies LLC
- Rajan Paudel
- G11 - INFORMATION STORAGE
Information Patent Grant
Select gate defect detection
- Patent number 9,530,514
- Issue date Dec 27, 2016
- SanDisk Technologies LLC
- Jagdish Sabde
- G11 - INFORMATION STORAGE
Information Patent Grant
Determination of word line to word line shorts between adjacent blocks
- Patent number 9,514,835
- Issue date Dec 6, 2016
- SanDisk Technologies LLC
- Sagar Magia
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive multi-page programming methods and apparatus for non-volat...
- Patent number 9,496,040
- Issue date Nov 15, 2016
- SanDisk Technologies LLC
- Rajan Paudel
- G11 - INFORMATION STORAGE
Information Patent Grant
Determination of word line to local source line shorts
- Patent number 9,484,086
- Issue date Nov 1, 2016
- SanDisk Technologies LLC
- Sagar Magia
- G11 - INFORMATION STORAGE
Information Patent Grant
AC stress mode to screen out word line to word line shorts
- Patent number 9,460,809
- Issue date Oct 4, 2016
- SanDisk Technologies LLC
- Sagar Magia
- G11 - INFORMATION STORAGE
Information Patent Grant
Block and zone erase algorithm for memory
- Patent number 9,449,698
- Issue date Sep 20, 2016
- SanDisk Technologies LLC
- Rajan Paudel
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory with multi-word line select for defect detectio...
- Patent number 9,449,694
- Issue date Sep 20, 2016
- SanDisk Technologies LLC
- Rajan Paudel
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods to improve programming of slow cells
- Patent number 9,269,446
- Issue date Feb 23, 2016
- SanDisk Technologies Inc.
- Sagar Magia
- G11 - INFORMATION STORAGE
Information Patent Grant
AC stress methods to screen out bit line defects
- Patent number 9,240,249
- Issue date Jan 19, 2016
- SanDisk Technologies Inc.
- Jagdish Sabde
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for detection and treating memory hole to local intercon...
- Patent number 9,224,502
- Issue date Dec 29, 2015
- SanDisk Technologies Inc.
- Jagdish Sabde
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for detecting broken word lines in non-volatile memories
- Patent number 9,202,593
- Issue date Dec 1, 2015
- SanDisk Technologies Inc.
- Sagar Magia
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
PARITY RELOCATION FOR REDUCING TEMPERATURE THROTTLING
- Publication number 20190317672
- Publication date Oct 17, 2019
- Western Digital Technologies, Inc.
- Daniel Joseph Linnen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHODS FOR RETICLE CONFIGURATION
- Publication number 20190187553
- Publication date Jun 20, 2019
- SanDisk Technologies LLC
- Daniel J. Linnen
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
PARTIAL MEMORY DIE WITH INTER-PLANE RE-MAPPING
- Publication number 20190129861
- Publication date May 2, 2019
- SanDisk Technologies LLC
- Daniel Linnen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARTIAL MEMORY DIE
- Publication number 20190130978
- Publication date May 2, 2019
- SanDisk Technologies LLC
- Daniel Linnen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH-SPEED DATA PATH TESTING TECHNIQUES FOR NON-VOLATILE MEMORY
- Publication number 20180350445
- Publication date Dec 6, 2018
- SanDisk Technologies LLC
- Daniel Linnen
- G11 - INFORMATION STORAGE
Information Patent Application
NAND STRUCTURE WITH TIER SELECT GATE TRANSISTORS
- Publication number 20170287566
- Publication date Oct 5, 2017
- SanDisk Technologies LLC
- Jagdish Sabde
- G11 - INFORMATION STORAGE
Information Patent Application
DETERMINATION OF WORD LINE TO WORD LINE SHORTS BETWEEN ADJACENT BLOCKS
- Publication number 20170025182
- Publication date Jan 26, 2017
- SanDisk Technologies LLC
- Jagdish Sabde
- G11 - INFORMATION STORAGE
Information Patent Application
STRESS PATTERNS TO DETECT SHORTS IN THREE DIMENSIONAL NON-VOLATILE...
- Publication number 20160343454
- Publication date Nov 24, 2016
- SANDISK TECHNOLOGIES INC.
- Jayavel Pachamuthu
- G11 - INFORMATION STORAGE
Information Patent Application
CURRENT BASED Detection and Recording of Memory Hole-Interconnect S...
- Publication number 20160300607
- Publication date Oct 13, 2016
- SANDISK TECHNOLOGIES INC.
- Sagar Magia
- G11 - INFORMATION STORAGE
Information Patent Application
Word Line Look Ahead Read For Word Line To Word Line Short Detection
- Publication number 20160260495
- Publication date Sep 8, 2016
- SANDISK TECHNOLOGIES INC.
- Rajan Paudel
- G11 - INFORMATION STORAGE
Information Patent Application
Techniques for Determining Local Interconnect Defects
- Publication number 20160232985
- Publication date Aug 11, 2016
- SANDISK TECHNOLOGIES INC.
- Jagdish Sabde
- G01 - MEASURING TESTING
Information Patent Application
ADAPTIVE MULTI-PAGE PROGRAMMING METHODS AND APPARATUS FOR NON-VOLAT...
- Publication number 20160217857
- Publication date Jul 28, 2016
- SANDISK TECHNOLOGIES INC.
- Rajan Paudel
- G11 - INFORMATION STORAGE
Information Patent Application
Block Level Local Column Redundancy Methods for Higher Yield
- Publication number 20160124664
- Publication date May 5, 2016
- SANDISK TECHNOLOGIES INC.
- Jagdish Sabde
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Erase Stress and Delta Erase Loop Count Methods for Various Fail Mo...
- Publication number 20160125956
- Publication date May 5, 2016
- SANDISK TECHNOLOGIES INC.
- Sagar Magia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Non-Volatile Memory with Multi-Word Line Select for Defect Detectio...
- Publication number 20160071594
- Publication date Mar 10, 2016
- SANDISK TECHNOLOGIES INC.
- Rajan Paudel
- G11 - INFORMATION STORAGE
Information Patent Application
Determination of Word Line to Word Line Shorts Between Adjacent Blocks
- Publication number 20160012904
- Publication date Jan 14, 2016
- SANDISK TECHNOLOGIES INC.
- Jagdish Sabde
- G11 - INFORMATION STORAGE
Information Patent Application
Determination of Bit Line to Low Voltage Signal Shorts
- Publication number 20160012915
- Publication date Jan 14, 2016
- SANDISK TECHNOLOGIES INC.
- Sagar Magia
- G11 - INFORMATION STORAGE
Information Patent Application
AC Stress Mode to Screen Out Word Line to Word Line Shorts
- Publication number 20160012913
- Publication date Jan 14, 2016
- SANDISK TECHNOLOGIES INC.
- Sagar Magia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Determination of Word Line to Local Source Line Shorts
- Publication number 20160012914
- Publication date Jan 14, 2016
- SANDISK TECHNOLOGIES INC.
- Sagar Magia
- G11 - INFORMATION STORAGE

Jagdish Sabde

Person

Patents Grantslast 30 patents

Partial memory die with inter-plane re-mapping

Parity relocation for reducing temperature throttling

Partial memory die

High-speed data path testing techniques for non-volatile memory

Techniques for determining local interconnect defects

NAND structure with tier select gate transistors

Erase stress and delta erase loop count methods for various fail mo...

Multi-tier memory stack structure containing non-overlapping suppor...

Stress patterns to detect shorts in three dimensional non-volatile...

Determination of word line to word line shorts between adjacent blocks

Current based detection and recording of memory hole-interconnect s...

Word line look ahead read for word line to word line short detection

Select gate defect detection

Determination of word line to word line shorts between adjacent blocks

Adaptive multi-page programming methods and apparatus for non-volat...

Determination of word line to local source line shorts

AC stress mode to screen out word line to word line shorts

Block and zone erase algorithm for memory

Non-volatile memory with multi-word line select for defect detectio...

Methods to improve programming of slow cells

AC stress methods to screen out bit line defects

Techniques for detection and treating memory hole to local intercon...

Techniques for detecting broken word lines in non-volatile memories

Patents Applicationslast 30 patents

PARITY RELOCATION FOR REDUCING TEMPERATURE THROTTLING

APPARATUS AND METHODS FOR RETICLE CONFIGURATION

PARTIAL MEMORY DIE WITH INTER-PLANE RE-MAPPING

PARTIAL MEMORY DIE

HIGH-SPEED DATA PATH TESTING TECHNIQUES FOR NON-VOLATILE MEMORY

NAND STRUCTURE WITH TIER SELECT GATE TRANSISTORS

DETERMINATION OF WORD LINE TO WORD LINE SHORTS BETWEEN ADJACENT BLOCKS

STRESS PATTERNS TO DETECT SHORTS IN THREE DIMENSIONAL NON-VOLATILE...

CURRENT BASED Detection and Recording of Memory Hole-Interconnect S...

Word Line Look Ahead Read For Word Line To Word Line Short Detection

Techniques for Determining Local Interconnect Defects

ADAPTIVE MULTI-PAGE PROGRAMMING METHODS AND APPARATUS FOR NON-VOLAT...

Block Level Local Column Redundancy Methods for Higher Yield

Erase Stress and Delta Erase Loop Count Methods for Various Fail Mo...

Non-Volatile Memory with Multi-Word Line Select for Defect Detectio...

Determination of Word Line to Word Line Shorts Between Adjacent Blocks

Determination of Bit Line to Low Voltage Signal Shorts

AC Stress Mode to Screen Out Word Line to Word Line Shorts

Determination of Word Line to Local Source Line Shorts