James A McCall

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Techniques to couple high bandwidth memory device on silicon substr...
- Patent number 12,087,352
- Issue date Sep 10, 2024
- Tahoe Research, LTD.
- Chong J. Zhao
- G11 - INFORMATION STORAGE
Information Patent Grant
Package pin pattern for device-to-device connection
- Patent number 12,073,906
- Issue date Aug 27, 2024
- Intel Corporation
- Chong J. Zhao
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques to couple high bandwidth memory device on silicon substr...
- Patent number 11,776,619
- Issue date Oct 3, 2023
- Tahoe Research, LTD.
- Chong J. Zhao
- G11 - INFORMATION STORAGE
Information Patent Grant
Electrically coupled trace routing configuration in multiple layers
- Patent number 11,657,862
- Issue date May 23, 2023
- Intel Corporation
- Rogelio Alfonso Moreyra Gonzalez
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated memory coplanar transmission line package having ground...
- Patent number 11,569,161
- Issue date Jan 31, 2023
- Intel Corporation
- Chong Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques to couple high bandwidth memory device on silicon substr...
- Patent number 11,557,333
- Issue date Jan 17, 2023
- Tahoe Research, LTD.
- Chong J. Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Applying chip select for memory device identification and power man...
- Patent number 11,335,395
- Issue date May 17, 2022
- Intel Corporation
- Christopher E. Cox
- G11 - INFORMATION STORAGE
Information Patent Grant
Discrete circuit having cross-talk noise cancellation circuitry and...
- Patent number 11,116,072
- Issue date Sep 7, 2021
- Intel Corporation
- Jun Liao
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
DDR memory bus with a reduced data strobe signal preamble timespan
- Patent number 11,074,959
- Issue date Jul 27, 2021
- Intel Corporation
- James A. McCall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques to couple high bandwidth memory device on silicon substr...
- Patent number 11,056,179
- Issue date Jul 6, 2021
- Intel Corporation
- Chong J. Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Connector with active circuit
- Patent number 10,965,047
- Issue date Mar 30, 2021
- Intel Corporation
- Jong-Ru Guo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High bandwidth DIMM
- Patent number 10,963,404
- Issue date Mar 30, 2021
- Intel Corporation
- James A. McCall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Packed interconnect structure with reduced cross coupled noise
- Patent number 10,950,536
- Issue date Mar 16, 2021
- Intel Corporation
- Zhen Zhou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus, method and system for providing termination for multiple...
- Patent number 10,943,640
- Issue date Mar 9, 2021
- Intel Corporation
- Kuljit S. Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DIMM for a high bandwidth memory channel
- Patent number 10,884,958
- Issue date Jan 5, 2021
- Intel Corporation
- Rajat Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Applying chip select for memory device identification and power man...
- Patent number 10,839,887
- Issue date Nov 17, 2020
- Intel Corporation
- Christopher E. Cox
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic bus inversion with programmable termination level to mainta...
- Patent number 10,802,996
- Issue date Oct 13, 2020
- Intel Corporation
- Christopher P. Mozak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device, system and method to mitigate signal noise in communication...
- Patent number 10,729,002
- Issue date Jul 28, 2020
- Intel Corporation
- Jun Liao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Printed circuit board (PCB) with three-dimensional interconnects to...
- Patent number 10,617,000
- Issue date Apr 7, 2020
- Intel Corporation
- Daqiao Du
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques to access or operate a dual in-line memory module via mu...
- Patent number 10,592,445
- Issue date Mar 17, 2020
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Impedance compensation based on detecting sensor data
- Patent number 10,552,285
- Issue date Feb 4, 2020
- Intel Corporation
- James A. McCall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DDR memory bus with a reduced data strobe signal preamble timespan
- Patent number 10,541,018
- Issue date Jan 21, 2020
- Intel Corporation
- James A. McCall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory channel driver with echo cancellation
- Patent number 10,528,515
- Issue date Jan 7, 2020
- Intel Corporation
- Qin Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory channel having more than one DIMM per motherboard DIMM conne...
- Patent number 10,467,160
- Issue date Nov 5, 2019
- Intel Corporation
- Xiang Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic bus inversion with programmable termination level to mainta...
- Patent number 10,437,746
- Issue date Oct 8, 2019
- Intel Corporation
- Christopher P. Mozak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques to access or operate a dual in-line memory module via mu...
- Patent number 10,146,711
- Issue date Dec 4, 2018
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reconfigurable clocking architecture
- Patent number 10,134,463
- Issue date Nov 20, 2018
- Intel Corporation
- Mozhgan Mansuri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus, method and system for providing termination for multiple...
- Patent number 10,121,528
- Issue date Nov 6, 2018
- Intel Corporation
- George Vergis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple rank high bandwidth memory
- Patent number 10,079,052
- Issue date Sep 18, 2018
- Intel Corporation
- Christopher P. Mozak
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic bus inversion with programmable termination level to mainta...
- Patent number 10,031,868
- Issue date Jul 24, 2018
- Intel Corporation
- Christopher P. Mozak
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
TECHNIQUES TO COUPLE HIGH BANDWIDTH MEMORY DEVICE ON SILICON SUBSTR...
- Publication number 20250006250
- Publication date Jan 2, 2025
- Tahoe Research, Ltd.
- Chong J. ZHAO
- G11 - INFORMATION STORAGE
Information Patent Application
CONNECTOR PINS FOR REDUCING CROSSTALK
- Publication number 20240145996
- Publication date May 2, 2024
- Intel Corporation
- Xiang LI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DYNAMIC SWITCH FOR MEMORY DEVICES
- Publication number 20240028531
- Publication date Jan 25, 2024
- Intel Corporation
- John R. DREW
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES TO COUPLE HIGH BANDWIDTH MEMORY DEVICE ON SILICON SUBSTR...
- Publication number 20240029785
- Publication date Jan 25, 2024
- Tahoe Research, Ltd.
- Chong J. ZHAO
- G11 - INFORMATION STORAGE
Information Patent Application
HYBRID SEARCH TO TRAIN MEMORY AND HIGH-SPEED INPUT/OUTPUT INTERFACES
- Publication number 20230214669
- Publication date Jul 6, 2023
- Intel Corporation
- Wenzhi WANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES TO COUPLE HIGH BANDWIDTH MEMORY DEVICE ON SILICON SUBSTR...
- Publication number 20230145937
- Publication date May 11, 2023
- Tahoe Research, Ltd.
- Chong J. ZHAO
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-CHANNEL MEMORY MODULE
- Publication number 20230044892
- Publication date Feb 9, 2023
- Intel Corporation
- Xiang LI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRACE DESIGN TO REDUCE THE CONNECTOR CROSSTALK
- Publication number 20220418090
- Publication date Dec 29, 2022
- Intel Corporation
- Landon HANKS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
UNIDIRECTIONAL COMMAND BUS PHASE DRIFT COMPENSATION
- Publication number 20220393682
- Publication date Dec 8, 2022
- Intel Corporation
- James A. McCALL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT BOARD TO REDUCE FAR END CROSS TALK
- Publication number 20220304142
- Publication date Sep 22, 2022
- Intel Corporation
- Xiang LI
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
SHIELDED SOCKET PIN FOR DEVICE-TO-DEVICE CONNECTION
- Publication number 20220263262
- Publication date Aug 18, 2022
- Intel Corporation
- Landon HANKS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ROUTING FOR CROSSTALK REDUCTION IN HIGH FREQUENCY COMMUNICA...
- Publication number 20220122929
- Publication date Apr 21, 2022
- Intel Corporation
- Xiang LI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PIN CONFIGURATION FOR DEVICE-TO-DEVICE CONNECTION
- Publication number 20220102917
- Publication date Mar 31, 2022
- Intel Corporation
- Xiang LI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY MODULE AND CONNECTOR FORM FACTOR TO REDUCE CROSSTALK
- Publication number 20210408704
- Publication date Dec 30, 2021
- Intel Corporation
- Xiang Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES TO COUPLE HIGH BANDWIDTH MEMORY DEVICE ON SILICON SUBSTR...
- Publication number 20210335414
- Publication date Oct 28, 2021
- Intel Corporation
- Chong J. ZHAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED MEMORY CHIP SOLUTION WITH REDUCED PACKAGE INPUTS/OUTPUTS (I...
- Publication number 20210335393
- Publication date Oct 28, 2021
- Intel Corporation
- Chong J. ZHAO
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS, SYSTEM AND METHOD TO DETECT AND IMPROVE AN INPUT CLOCK P...
- Publication number 20210312972
- Publication date Oct 7, 2021
- Arvind A. Kumar
- G11 - INFORMATION STORAGE
Information Patent Application
BUFFER THAT SUPPORTS BURST TRANSFERS HAVING PARALLEL CRC AND DATA T...
- Publication number 20210279128
- Publication date Sep 9, 2021
- Intel Corporation
- James A. McCALL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTION OF ERROR CHECKING AND CORRECTION (ECC) BITS TO ALLOCAT...
- Publication number 20210141692
- Publication date May 13, 2021
- Intel Corporation
- Rajat AGARWAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PACKAGE PIN PATTERN FOR DEVICE-TO-DEVICE CONNECTION
- Publication number 20210074333
- Publication date Mar 11, 2021
- Intel Corporation
- Chong J. ZHAO
- G11 - INFORMATION STORAGE
Information Patent Application
APPLYING CHIP SELECT FOR MEMORY DEVICE IDENTIFICATION AND POWER MAN...
- Publication number 20210020224
- Publication date Jan 21, 2021
- Intel Corporation
- Christopher E. COX
- G11 - INFORMATION STORAGE
Information Patent Application
TRANSMIT CROSSTALK CANCELLATION SYSTEM
- Publication number 20200313722
- Publication date Oct 1, 2020
- Intel Corporation
- James Alexander McCall
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
ELECTRICALLY COUPLED TRACE ROUTING CONFIGURATION IN MULTIPLE LAYERS
- Publication number 20200302978
- Publication date Sep 24, 2020
- Intel Corporation
- Rogelio Alfonso MOREYRA GONZALEZ
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
DDR MEMORY BUS WITH A REDUCED DATA STROBE SIGNAL PREAMBLE TIMESPAN
- Publication number 20200286543
- Publication date Sep 10, 2020
- Intel Corporation
- James A. McCALL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED MEMORY COPLANAR TRANSMISSION LINE PACKAGE TO EXTEND MEMO...
- Publication number 20200243433
- Publication date Jul 30, 2020
- Chong ZHAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES TO COUPLE HIGH BANDWIDTH MEMORY DEVICE ON SILICON SUBSTR...
- Publication number 20200143870
- Publication date May 7, 2020
- Intel Corporation
- Chong J. ZHAO
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMIC BUS INVERSION WITH PROGRAMMABLE TERMINATION LEVEL TO MAINTA...
- Publication number 20200081852
- Publication date Mar 12, 2020
- Intel Corporation
- Christopher P. MOZAK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPLYING CHIP SELECT FOR MEMORY DEVICE IDENTIFICATION AND POWER MAN...
- Publication number 20190392886
- Publication date Dec 26, 2019
- Intel Corporation
- Christopher E. COX
- G11 - INFORMATION STORAGE
Information Patent Application
DEVICE, SYSTEM AND METHOD TO MITIGATE SIGNAL NOISE IN COMMUNICATION...
- Publication number 20190342990
- Publication date Nov 7, 2019
- Jun Liao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CONNECTOR WITH ACTIVE CIRCUIT
- Publication number 20190288421
- Publication date Sep 19, 2019
- Intel Corporation
- Jong-Ru Guo
- H01 - BASIC ELECTRIC ELEMENTS

James A McCall

Person

Patents Grantslast 30 patents

Techniques to couple high bandwidth memory device on silicon substr...

Package pin pattern for device-to-device connection

Techniques to couple high bandwidth memory device on silicon substr...

Electrically coupled trace routing configuration in multiple layers

Integrated memory coplanar transmission line package having ground...

Techniques to couple high bandwidth memory device on silicon substr...

Applying chip select for memory device identification and power man...

Discrete circuit having cross-talk noise cancellation circuitry and...

DDR memory bus with a reduced data strobe signal preamble timespan

Techniques to couple high bandwidth memory device on silicon substr...

Connector with active circuit

High bandwidth DIMM

Packed interconnect structure with reduced cross coupled noise

Apparatus, method and system for providing termination for multiple...

DIMM for a high bandwidth memory channel

Applying chip select for memory device identification and power man...

Dynamic bus inversion with programmable termination level to mainta...

Device, system and method to mitigate signal noise in communication...

Printed circuit board (PCB) with three-dimensional interconnects to...

Techniques to access or operate a dual in-line memory module via mu...

Impedance compensation based on detecting sensor data

DDR memory bus with a reduced data strobe signal preamble timespan

Memory channel driver with echo cancellation

Memory channel having more than one DIMM per motherboard DIMM conne...

Dynamic bus inversion with programmable termination level to mainta...

Techniques to access or operate a dual in-line memory module via mu...

Reconfigurable clocking architecture

Apparatus, method and system for providing termination for multiple...

Multiple rank high bandwidth memory

Dynamic bus inversion with programmable termination level to mainta...

Patents Applicationslast 30 patents

TECHNIQUES TO COUPLE HIGH BANDWIDTH MEMORY DEVICE ON SILICON SUBSTR...

CONNECTOR PINS FOR REDUCING CROSSTALK

DYNAMIC SWITCH FOR MEMORY DEVICES

TECHNIQUES TO COUPLE HIGH BANDWIDTH MEMORY DEVICE ON SILICON SUBSTR...

HYBRID SEARCH TO TRAIN MEMORY AND HIGH-SPEED INPUT/OUTPUT INTERFACES

TECHNIQUES TO COUPLE HIGH BANDWIDTH MEMORY DEVICE ON SILICON SUBSTR...

MULTI-CHANNEL MEMORY MODULE

TRACE DESIGN TO REDUCE THE CONNECTOR CROSSTALK

UNIDIRECTIONAL COMMAND BUS PHASE DRIFT COMPENSATION

CIRCUIT BOARD TO REDUCE FAR END CROSS TALK

SHIELDED SOCKET PIN FOR DEVICE-TO-DEVICE CONNECTION

PACKAGE ROUTING FOR CROSSTALK REDUCTION IN HIGH FREQUENCY COMMUNICA...

PIN CONFIGURATION FOR DEVICE-TO-DEVICE CONNECTION

MEMORY MODULE AND CONNECTOR FORM FACTOR TO REDUCE CROSSTALK

TECHNIQUES TO COUPLE HIGH BANDWIDTH MEMORY DEVICE ON SILICON SUBSTR...

STACKED MEMORY CHIP SOLUTION WITH REDUCED PACKAGE INPUTS/OUTPUTS (I...

APPARATUS, SYSTEM AND METHOD TO DETECT AND IMPROVE AN INPUT CLOCK P...

BUFFER THAT SUPPORTS BURST TRANSFERS HAVING PARALLEL CRC AND DATA T...

DISTRIBUTION OF ERROR CHECKING AND CORRECTION (ECC) BITS TO ALLOCAT...

PACKAGE PIN PATTERN FOR DEVICE-TO-DEVICE CONNECTION

APPLYING CHIP SELECT FOR MEMORY DEVICE IDENTIFICATION AND POWER MAN...

TRANSMIT CROSSTALK CANCELLATION SYSTEM

ELECTRICALLY COUPLED TRACE ROUTING CONFIGURATION IN MULTIPLE LAYERS

DDR MEMORY BUS WITH A REDUCED DATA STROBE SIGNAL PREAMBLE TIMESPAN

INTEGRATED MEMORY COPLANAR TRANSMISSION LINE PACKAGE TO EXTEND MEMO...

TECHNIQUES TO COUPLE HIGH BANDWIDTH MEMORY DEVICE ON SILICON SUBSTR...

DYNAMIC BUS INVERSION WITH PROGRAMMABLE TERMINATION LEVEL TO MAINTA...

APPLYING CHIP SELECT FOR MEMORY DEVICE IDENTIFICATION AND POWER MAN...

DEVICE, SYSTEM AND METHOD TO MITIGATE SIGNAL NOISE IN COMMUNICATION...

CONNECTOR WITH ACTIVE CIRCUIT