James D. Barnette

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Using time-to-digital converters to delay signals with high accurac...
- Patent number 12,019,406
- Issue date Jun 25, 2024
- Skyworks Solutions, Inc.
- Krishnan Balakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using time-to-digital converters to delay signals with high accurac...
- Patent number 11,526,135
- Issue date Dec 13, 2022
- Skyworks Solutions, Inc.
- Krishnan Balakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synchronization of clock signals generated using output dividers
- Patent number 11,342,926
- Issue date May 24, 2022
- Silicon Laboratories Inc.
- James D. Barnette
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for generation of independent clock signals from the same os...
- Patent number 11,245,406
- Issue date Feb 8, 2022
- Silicon Laboratories Inc.
- Harihara Subramanian Ranganathan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Spur and quantization noise cancellation for PLLS with non-linear p...
- Patent number 11,038,521
- Issue date Jun 15, 2021
- Silicon Laboratories Inc.
- Aslamali A. Rafi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Synchronization of clock signals generated using output dividers
- Patent number 10,951,216
- Issue date Mar 16, 2021
- Silicon Laboratories Inc.
- James D. Barnette
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Fractional divider with error correction
- Patent number 10,826,507
- Issue date Nov 3, 2020
- Silicon Laboratories Inc.
- Xue-Mei Gong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Accurate and reliable digital PLL lock indicator
- Patent number 10,819,354
- Issue date Oct 27, 2020
- Silicon Laboratories Inc.
- Kannanthodath V. Jayakumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Use of a virtual clock in a PLL to maintain a closed loop system
- Patent number 10,727,845
- Issue date Jul 28, 2020
- Silicon Laboratories Inc.
- Krishnan Balakrishnan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for switching master/slave timing in a 1000Base-T link witho...
- Patent number RE48130
- Issue date Jul 28, 2020
- Microsemi Storage Solutions, Inc.
- James D Barnette
Information Patent Grant
Reference clock frequency change handling in a phase-locked loop
- Patent number 10,727,844
- Issue date Jul 28, 2020
- Silicon Laboratories Inc.
- Xue-Mei Gong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Gradual frequency transition with a frequency step
- Patent number 10,693,475
- Issue date Jun 23, 2020
- Silicon Laboratories Inc.
- Xue-Mei Gong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Locking a PLL to the nearest edge of the input clock when the input...
- Patent number 10,651,862
- Issue date May 12, 2020
- Silicon Laboratories Inc.
- James D. Barnette
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Relative frequency offset error and phase error detection for clocks
- Patent number 10,608,649
- Issue date Mar 31, 2020
- Silicon Laboratories Inc.
- Kannanthodath V. Jayakumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for switching master/slave timing in a 1000BASE-T link witho...
- Patent number 8,923,341
- Issue date Dec 30, 2014
- Vitesse Semiconductor Corporation
- James D. Barnette
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method for squelching a recovered clock in an ethernet n...
- Patent number 8,179,901
- Issue date May 15, 2012
- Vitesse Semiconductor Corporation
- Jason C. Rock
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Resampler for a bit pump and method of resampling a signal associat...
- Patent number 7,542,536
- Issue date Jun 2, 2009
- Alcatel-Lucent USA Inc.
- James D. Barnette
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Resampler for a bit pump and method of resampling a signal associat...
- Patent number 6,973,146
- Issue date Dec 6, 2005
- Lucent Technologies Inc.
- James D. Barnette
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Interpolator, a resampler employing the interpolator and method of...
- Patent number 6,970,511
- Issue date Nov 29, 2005
- Lucent Technologies Inc.
- James D. Barnette
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuits, system, and methods for processing multiple data streams
- Patent number 6,055,619
- Issue date Apr 25, 2000
- Cirrus Logic, Inc.
- Gregory Allen North
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
USING TIME-TO-DIGITAL CONVERTERS TO DELAY SIGNALS WITH HIGH ACCURAC...
- Publication number 20250021055
- Publication date Jan 16, 2025
- Skyworks Solutions, Inc.
- Krishnan Balakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND AN APPARATUS FOR GENERATING AN OUTPUT CLOCK IN A MULTI-L...
- Publication number 20240297656
- Publication date Sep 5, 2024
- Skyworks Solutions, Inc.
- Xue-Mei Gong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
USING TIME-TO-DIGITAL CONVERTERS TO DELAY SIGNALS WITH HIGH ACCURAC...
- Publication number 20230185249
- Publication date Jun 15, 2023
- Skyworks Solutions, Inc.
- Krishnan Balakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR GENERATION OF INDEPENDENT CLOCK SIGNALS FROM THE SAME OS...
- Publication number 20210409031
- Publication date Dec 30, 2021
- Silicon Laboratories Inc.
- Harihara Subramanian Ranganathan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYNCHRONIZATION OF CLOCK SIGNALS GENERATED USING OUTPUT DIVIDERS
- Publication number 20210184687
- Publication date Jun 17, 2021
- Silicon Laboratories Inc.
- James D. Barnette
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
USING TIME-TO-DIGITAL CONVERTERS TO DELAY SIGNALS WITH HIGH ACCURAC...
- Publication number 20200379412
- Publication date Dec 3, 2020
- Silicon Laboratories Inc.
- Krishnan Balakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FRACTIONAL DIVIDER WITH ERROR CORRECTION
- Publication number 20200358449
- Publication date Nov 12, 2020
- Silicon Laboratories Inc.
- Xue-Mei Gong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ACCURATE AND RELIABLE DIGITAL PLL LOCK INDICATOR
- Publication number 20200162081
- Publication date May 21, 2020
- Silicon Laboratories Inc.
- Kannanthodath V. Jayakumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYSTEM AND METHOD FOR SQUELCHING A RECOVERED CLOCK IN AN ETHERNET N...
- Publication number 20120224493
- Publication date Sep 6, 2012
- Vitesse Semiconductor Corporation
- Jason C. Rock
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD FOR SWITCHING MASTER/SLAVE TIMING IN A 1000BASE-T LINK WITHO...
- Publication number 20110170645
- Publication date Jul 14, 2011
- James D. Barnette
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYSTEM AND METHOD FOR DETECTING EARLY LINK FAILURE IN AN ETHERNET N...
- Publication number 20090201821
- Publication date Aug 13, 2009
- James D. Barnette
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYSTEM AND METHOD FOR SQUELCHING A RECOVERED CLOCK IN AN ETHERNET N...
- Publication number 20090201924
- Publication date Aug 13, 2009
- Jason C. Rock
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Resampler for a bit pump and method of resampling a signal associat...
- Publication number 20060023821
- Publication date Feb 2, 2006
- Lucent Technologies Inc.
- James D. Barnette
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

James D. Barnette

Person

Patents Grantslast 30 patents

Using time-to-digital converters to delay signals with high accurac...

Using time-to-digital converters to delay signals with high accurac...

Synchronization of clock signals generated using output dividers

Method for generation of independent clock signals from the same os...

Spur and quantization noise cancellation for PLLS with non-linear p...

Synchronization of clock signals generated using output dividers

Fractional divider with error correction

Accurate and reliable digital PLL lock indicator

Use of a virtual clock in a PLL to maintain a closed loop system

Method for switching master/slave timing in a 1000Base-T link witho...

Reference clock frequency change handling in a phase-locked loop

Gradual frequency transition with a frequency step

Locking a PLL to the nearest edge of the input clock when the input...

Relative frequency offset error and phase error detection for clocks

Method for switching master/slave timing in a 1000BASE-T link witho...

System and method for squelching a recovered clock in an ethernet n...

Resampler for a bit pump and method of resampling a signal associat...

Resampler for a bit pump and method of resampling a signal associat...

Interpolator, a resampler employing the interpolator and method of...

Circuits, system, and methods for processing multiple data streams

Patents Applicationslast 30 patents

USING TIME-TO-DIGITAL CONVERTERS TO DELAY SIGNALS WITH HIGH ACCURAC...

METHOD AND AN APPARATUS FOR GENERATING AN OUTPUT CLOCK IN A MULTI-L...

USING TIME-TO-DIGITAL CONVERTERS TO DELAY SIGNALS WITH HIGH ACCURAC...

METHOD FOR GENERATION OF INDEPENDENT CLOCK SIGNALS FROM THE SAME OS...

SYNCHRONIZATION OF CLOCK SIGNALS GENERATED USING OUTPUT DIVIDERS

USING TIME-TO-DIGITAL CONVERTERS TO DELAY SIGNALS WITH HIGH ACCURAC...

FRACTIONAL DIVIDER WITH ERROR CORRECTION

ACCURATE AND RELIABLE DIGITAL PLL LOCK INDICATOR

SYSTEM AND METHOD FOR SQUELCHING A RECOVERED CLOCK IN AN ETHERNET N...

METHOD FOR SWITCHING MASTER/SLAVE TIMING IN A 1000BASE-T LINK WITHO...

SYSTEM AND METHOD FOR DETECTING EARLY LINK FAILURE IN AN ETHERNET N...

SYSTEM AND METHOD FOR SQUELCHING A RECOVERED CLOCK IN AN ETHERNET N...

Resampler for a bit pump and method of resampling a signal associat...