James Hadley

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Scheduler implementing dependency matrix having restricted entries
- Patent number 10,235,180
- Issue date Mar 19, 2019
- Intel Corporation
- Srikanth T. Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Physical reference list for tracking physical register sharing
- Patent number 9,733,939
- Issue date Aug 15, 2017
- Intel Corporation
- Vijaykumar Balaram Kadgi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus including a stall counter to bias processing element sele...
- Patent number 9,524,191
- Issue date Dec 20, 2016
- Intel Corporation
- Morris Marden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Copy-on-write buffer for restoring program code from a speculative...
- Patent number 9,182,986
- Issue date Nov 10, 2015
- Intel Corporation
- Ravi Rajwar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing thread fairness by biasing selection away from a stalling...
- Patent number 8,521,993
- Issue date Aug 27, 2013
- Intel Corporation
- Morris Marden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing multiple threads in a single pipeline
- Patent number 8,504,804
- Issue date Aug 6, 2013
- Intel Corporation
- Matthew Merten
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing thread fairness by biasing selection away from a stalling...
- Patent number 8,438,369
- Issue date May 7, 2013
- Intel Corporation
- Morris Marden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing multiple threads in a single pipeline
- Patent number 8,402,253
- Issue date Mar 19, 2013
- Intel Corporation
- Matthew Merten
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipelined instruction decoder for multi-threaded processors
- Patent number 6,931,516
- Issue date Aug 16, 2005
- Intel Corporation
- Jonathan P. Douglas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for multi-thread pipelined instruction decoder
- Patent number 6,609,193
- Issue date Aug 19, 2003
- Intel Corporation
- Jonathan P. Douglas
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
System, Apparatus And Method For A Hybrid Reservation Station For A...
- Publication number 20200409710
- Publication date Dec 31, 2020
- Srikanth Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING THREAD FAIRNESS IN A HYPER-THREADED MICROPROCESSOR
- Publication number 20170161106
- Publication date Jun 8, 2017
- Intel Corporation
- Morris Marden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Copy-On-Write Buffer For Restoring Program Code From A Speculative...
- Publication number 20140189315
- Publication date Jul 3, 2014
- Ravi RAJWAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scheduler Implementing Dependency Matrix Having Restricted Entries
- Publication number 20140181476
- Publication date Jun 26, 2014
- Srikanth T. Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Physical Reference List for Tracking Physical Register Sharing
- Publication number 20140095838
- Publication date Apr 3, 2014
- VIJAYKUMAR VIJAY KADGI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Renaming Mechanism in Microarchitecture
- Publication number 20140095814
- Publication date Apr 3, 2014
- MORRIS MARDEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Managing Multiple Threads In A Single Pipeline
- Publication number 20130013898
- Publication date Jan 10, 2013
- Matthew Merten
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING THREAD FAIRNESS IN A HYPER-THREADED MICROPROCESSOR
- Publication number 20110055524
- Publication date Mar 3, 2011
- Morris Marden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING THREAD FAIRNESS IN A HYPER-THREADED MICROPROCESSOR
- Publication number 20110055525
- Publication date Mar 3, 2011
- Morris Marden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Providing thread fairness in a hyper-threaded microprocessor
- Publication number 20080250233
- Publication date Oct 9, 2008
- Morris Marden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Managing multiple threads in a single pipeline
- Publication number 20080082796
- Publication date Apr 3, 2008
- Matthew Merten
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Early misprediction recovery through periodic checkpoints
- Publication number 20070043934
- Publication date Feb 22, 2007
- Intel Corporation
- Avinash Sodani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for multi-thread pipelined instruction decoder
- Publication number 20040107336
- Publication date Jun 3, 2004
- Jonathan P. Douglas
- G06 - COMPUTING CALCULATING COUNTING

James Hadley

Person

Patents Grantslast 30 patents

Scheduler implementing dependency matrix having restricted entries

Physical reference list for tracking physical register sharing

Apparatus including a stall counter to bias processing element sele...

Copy-on-write buffer for restoring program code from a speculative...

Providing thread fairness by biasing selection away from a stalling...

Managing multiple threads in a single pipeline

Providing thread fairness by biasing selection away from a stalling...

Managing multiple threads in a single pipeline

Pipelined instruction decoder for multi-threaded processors

Method and apparatus for multi-thread pipelined instruction decoder

Patents Applicationslast 30 patents

System, Apparatus And Method For A Hybrid Reservation Station For A...

PROVIDING THREAD FAIRNESS IN A HYPER-THREADED MICROPROCESSOR

Copy-On-Write Buffer For Restoring Program Code From A Speculative...

Scheduler Implementing Dependency Matrix Having Restricted Entries

Physical Reference List for Tracking Physical Register Sharing

Memory Renaming Mechanism in Microarchitecture

Managing Multiple Threads In A Single Pipeline

PROVIDING THREAD FAIRNESS IN A HYPER-THREADED MICROPROCESSOR

PROVIDING THREAD FAIRNESS IN A HYPER-THREADED MICROPROCESSOR

Providing thread fairness in a hyper-threaded microprocessor

Managing multiple threads in a single pipeline

Early misprediction recovery through periodic checkpoints

Method and apparatus for multi-thread pipelined instruction decoder