James Kimball

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method of treating metal and metal salts to enable thin layer depos...
- Patent number 7,670,645
- Issue date Mar 2, 2010
- LSI Corporation
- Sheldon Aronowitz
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method of vaporizing and ionizing metals for use in semiconductor p...
- Patent number 7,323,228
- Issue date Jan 29, 2008
- LSI Logic Corporation
- Sheldon Aronowitz
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Vaporization and ionization of metals for use in semiconductor proc...
- Patent number 7,084,408
- Issue date Aug 1, 2006
- LSI Logic Corporation
- James Kimball
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method of incorporating nitrogen into metal silicate based dielectr...
- Patent number 6,864,141
- Issue date Mar 8, 2005
- LSI Logic Corporation
- Wai Lo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thin gate dielectric for a CMOS transistor and method of fabricatio...
- Patent number 6,849,512
- Issue date Feb 1, 2005
- LSI Logic Corporation
- Wai Lo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for etching a controllable thickness of oxide on an integra...
- Patent number 6,759,337
- Issue date Jul 6, 2004
- LSI Logic Corporation
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
PROCESS FOR FORMING THIN GATE OXIDE WITH ENHANCED RELIABILITY BY NI...
- Patent number 6,413,881
- Issue date Jul 2, 2002
- LSI Logic Corporation
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of integrated circuit structure using one or more silicon...
- Patent number 6,331,468
- Issue date Dec 18, 2001
- LSI Logic Corporation
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FETs having lightly doped drain regions that are shaped with counte...
- Patent number 6,180,470
- Issue date Jan 30, 2001
- LSI Logic Corporation
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Composite semiconductor gate dielectrics
- Patent number 6,087,229
- Issue date Jul 11, 2000
- LSI Logic Corporation
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming re-entrant geometry for gate electrode of integ...
- Patent number 6,060,375
- Issue date May 9, 2000
- LSI Logic Corporation
- Jon Owyang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming variable thickness gate dielectrics
- Patent number 6,033,998
- Issue date Mar 7, 2000
- LSI Logic Corporation
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming retrograde well structures and punch-through barr...
- Patent number 5,963,801
- Issue date Oct 5, 1999
- LSI Logic Corporation
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for low energy implantation of semiconductor substrate usin...
- Patent number 5,904,551
- Issue date May 18, 1999
- LSI Logic Corporation
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for making group IV semiconductor substrate treated with on...
- Patent number 5,858,864
- Issue date Jan 12, 1999
- LSI Logic Corporation
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Oxide formed in semiconductor substrate by implantation of substrat...
- Patent number 5,739,580
- Issue date Apr 14, 1998
- LSI Logic Corporation
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate with controlled amount of noble gas ions to reduce channe...
- Patent number 5,717,238
- Issue date Feb 10, 1998
- LSI Logic Corporation
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Oxide formed in semiconductor substrate by implantation of substrat...
- Patent number 5,707,888
- Issue date Jan 13, 1998
- LSI Logic Corporation
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for making group IV semiconductor substrate treated with on...
- Patent number 5,654,210
- Issue date Aug 5, 1997
- LSI Logic Corporation
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Implantation of a semiconductor substrate with controlled amount of...
- Patent number 5,585,286
- Issue date Dec 17, 1996
- LSI Logic Corporation
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS

James Kimball

Person

Patents Grantslast 30 patents

Method of treating metal and metal salts to enable thin layer depos...

Method of vaporizing and ionizing metals for use in semiconductor p...

Vaporization and ionization of metals for use in semiconductor proc...

Method of incorporating nitrogen into metal silicate based dielectr...

Thin gate dielectric for a CMOS transistor and method of fabricatio...

Process for etching a controllable thickness of oxide on an integra...

PROCESS FOR FORMING THIN GATE OXIDE WITH ENHANCED RELIABILITY BY NI...

Formation of integrated circuit structure using one or more silicon...

FETs having lightly doped drain regions that are shaped with counte...

Composite semiconductor gate dielectrics

Process for forming re-entrant geometry for gate electrode of integ...

Method of forming variable thickness gate dielectrics

Method of forming retrograde well structures and punch-through barr...

Process for low energy implantation of semiconductor substrate usin...

Process for making group IV semiconductor substrate treated with on...

Oxide formed in semiconductor substrate by implantation of substrat...

Substrate with controlled amount of noble gas ions to reduce channe...

Oxide formed in semiconductor substrate by implantation of substrat...

Process for making group IV semiconductor substrate treated with on...

Implantation of a semiconductor substrate with controlled amount of...