James M. Dodd

Person

Citrus Heights, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Device and method for maximizing performance on a memory interface...
- Patent number 7,523,230
- Issue date Apr 21, 2009
- James M. Dodd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buffered writes and memory page control
- Patent number 7,469,316
- Issue date Dec 23, 2008
- Intel Corporation
- James M. Dodd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to improve multi-CPU system performance for ac...
- Patent number 7,404,047
- Issue date Jul 22, 2008
- Intel Corporation
- James M. Dodd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buffering and interleaving data transfer between a chipset and memo...
- Patent number 7,249,232
- Issue date Jul 24, 2007
- Intel Corporation
- John B. Halbert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Precharge suggestion
- Patent number 7,159,066
- Issue date Jan 2, 2007
- Intel Corporation
- James M. Dodd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory transaction ordering
- Patent number 7,120,765
- Issue date Oct 10, 2006
- Intel Corporation
- James M. Dodd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive page management
- Patent number 7,076,617
- Issue date Jul 11, 2006
- Intel Corporation
- James M. Dodd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual-port buffer-to-memory interface
- Patent number 7,024,518
- Issue date Apr 4, 2006
- Intel Corporation
- John B. Halbert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for controlling power states in a memory devic...
- Patent number 7,000,133
- Issue date Feb 14, 2006
- Intel Corporation
- James M. Dodd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory bus termination with memory unit having termination control
- Patent number 6,981,089
- Issue date Dec 27, 2005
- Intel Corporation
- James M. Dodd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mapping data masks in hardware by controller programming
- Patent number 6,957,307
- Issue date Oct 18, 2005
- Intel Corporation
- Robert J. Riesenman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Obtaining data mask mapping information
- Patent number 6,952,367
- Issue date Oct 4, 2005
- Intel Corporation
- Robert J. Riesenman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device and method for maximizing performance on a memory interface...
- Patent number 6,952,745
- Issue date Oct 4, 2005
- Intel Corporation
- James M. Dodd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for handling memory read return data from diff...
- Patent number 6,934,823
- Issue date Aug 23, 2005
- Intel Corporation
- Michael W. Williams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Obtaining data mask mapping information
- Patent number 6,925,013
- Issue date Aug 2, 2005
- Intel Corporation
- Robert J. Riesenman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Address decode
- Patent number 6,888,777
- Issue date May 3, 2005
- Intel Corporation
- James M. Dodd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for controlling data flow direction in a memory s...
- Patent number 6,862,653
- Issue date Mar 1, 2005
- Intel Corporation
- James M. Dodd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buffering data transfer between a chipset and memory modules
- Patent number 6,820,163
- Issue date Nov 16, 2004
- Intel Corporation
- James A. McCall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write clock and data window tuning based on rank select
- Patent number 6,804,764
- Issue date Oct 12, 2004
- Mircron Technology, Inc.
- Paul A. LaBerge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Obtaining data mask mapping information
- Patent number 6,801,459
- Issue date Oct 5, 2004
- Intel Corporation
- Robert J. Riesenman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system with burst length shorter than prefetch length
- Patent number 6,795,899
- Issue date Sep 21, 2004
- Intel Corporation
- James M. Dodd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Early power-down digital memory device and method
- Patent number 6,781,911
- Issue date Aug 24, 2004
- Intel Corporation
- Robert J. Riesenman
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for reducing the rate of commands being issued...
- Patent number 6,772,352
- Issue date Aug 3, 2004
- Intel Corporation
- Michael W. Williams
- G11 - INFORMATION STORAGE
Information Patent Grant
Device and method for maximizing performance on a memory interface...
- Patent number 6,766,385
- Issue date Jul 20, 2004
- Intel Corporation
- James M. Dodd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual-port buffer-to-memory interface
- Patent number 6,742,098
- Issue date May 25, 2004
- Intel Corporation
- John B. Halbert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for controlling of a memory subsystem installe...
- Patent number 6,725,349
- Issue date Apr 20, 2004
- Intel Corporation
- Brian K. Langendorf
- G11 - INFORMATION STORAGE
Information Patent Grant
Buffering and interleaving data transfer between a chipset and memo...
- Patent number 6,697,888
- Issue date Feb 24, 2004
- Intel Corporation
- John B. Halbert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory buffer arrangement
- Patent number 6,639,820
- Issue date Oct 28, 2003
- Intel Corporation
- Narendra S. Khandekar
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory module employing a junction circuit for point-to-point conne...
- Patent number 6,625,687
- Issue date Sep 23, 2003
- Intel Corporation
- John B. Halbert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for controlling power states of a memory device v...
- Patent number 6,618,791
- Issue date Sep 9, 2003
- Intel Corporation
- James M. Dodd
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Adaptive page management
- Publication number 20050071581
- Publication date Mar 31, 2005
- James M. Dodd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus to improve multi-CPU system performance for ac...
- Publication number 20040243768
- Publication date Dec 2, 2004
- James M. Dodd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Buffering and interleaving data transfer between a chipset and memo...
- Publication number 20040188704
- Publication date Sep 30, 2004
- Intel Corporation, a Delaware corporation
- John B. Halbert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Obtaining data mask mapping information
- Publication number 20040165446
- Publication date Aug 26, 2004
- Robert J. Riesenman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Buffered writes and memory page control
- Publication number 20040158677
- Publication date Aug 12, 2004
- James M. Dodd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Obtaining data mask mapping information
- Publication number 20040093471
- Publication date May 13, 2004
- Robert J. Riesenman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory transaction ordering
- Publication number 20040088450
- Publication date May 6, 2004
- James M. Dodd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Address decode
- Publication number 20040042320
- Publication date Mar 4, 2004
- James M. Dodd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Precharge suggestion
- Publication number 20040044832
- Publication date Mar 4, 2004
- James M. Dodd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System, apparatus, and method for a flexible DRAM architecture
- Publication number 20040015645
- Publication date Jan 22, 2004
- James M. Dodd
- G11 - INFORMATION STORAGE
Information Patent Application
Early power-down digital memory device and method
- Publication number 20030189868
- Publication date Oct 9, 2003
- Robert J. Riesenman
- G11 - INFORMATION STORAGE
Information Patent Application
Memory system with burst length shorter than prefetch length
- Publication number 20030182513
- Publication date Sep 25, 2003
- James M. Dodd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for controlling power states in a memory devic...
- Publication number 20030182588
- Publication date Sep 25, 2003
- James M. Dodd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mapping data masks in hardware by controller programming
- Publication number 20030182519
- Publication date Sep 25, 2003
- Robert J. Riesenman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Obtaining data mask mapping information
- Publication number 20030179605
- Publication date Sep 25, 2003
- Robert J. Riesenman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Write clock and data window tuning based on rank select
- Publication number 20030140208
- Publication date Jul 24, 2003
- Paul A. LaBerge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Device and method for maximizing performance on a memory interface...
- Publication number 20030131161
- Publication date Jul 10, 2003
- James M. Dodd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory bus termination with memory unit having termination control
- Publication number 20030126338
- Publication date Jul 3, 2003
- James M. Dodd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR INTEGRATING AND DETERMINING WHETHER A MEMO...
- Publication number 20030009616
- Publication date Jan 9, 2003
- BRIAN K. LANGENDORF
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for handling memory read return data from diff...
- Publication number 20020144071
- Publication date Oct 3, 2002
- Michael W. Williams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dual-port buffer-to-memory interface
- Publication number 20020112119
- Publication date Aug 15, 2002
- Intel Corporation
- John B. Halbert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TIER POINT-TO-POINT BUFFERED MEMORY INTERFACE
- Publication number 20020084458
- Publication date Jul 4, 2002
- John B. Halbert
- G06 - COMPUTING CALCULATING COUNTING

James M. Dodd

Person

Patents Grantslast 30 patents

Device and method for maximizing performance on a memory interface...

Buffered writes and memory page control

Method and apparatus to improve multi-CPU system performance for ac...

Buffering and interleaving data transfer between a chipset and memo...

Precharge suggestion

Memory transaction ordering

Adaptive page management

Dual-port buffer-to-memory interface

Method and apparatus for controlling power states in a memory devic...

Memory bus termination with memory unit having termination control

Mapping data masks in hardware by controller programming

Obtaining data mask mapping information

Device and method for maximizing performance on a memory interface...

Method and apparatus for handling memory read return data from diff...

Obtaining data mask mapping information

Address decode

System and method for controlling data flow direction in a memory s...

Buffering data transfer between a chipset and memory modules

Write clock and data window tuning based on rank select

Obtaining data mask mapping information

Memory system with burst length shorter than prefetch length

Early power-down digital memory device and method

Method and apparatus for reducing the rate of commands being issued...

Device and method for maximizing performance on a memory interface...

Dual-port buffer-to-memory interface

Method and apparatus for controlling of a memory subsystem installe...

Buffering and interleaving data transfer between a chipset and memo...

Memory buffer arrangement

Memory module employing a junction circuit for point-to-point conne...

System and method for controlling power states of a memory device v...

Patents Applicationslast 30 patents

Adaptive page management

Method and apparatus to improve multi-CPU system performance for ac...

Buffering and interleaving data transfer between a chipset and memo...

Obtaining data mask mapping information

Buffered writes and memory page control

Obtaining data mask mapping information

Memory transaction ordering

Address decode

Precharge suggestion

System, apparatus, and method for a flexible DRAM architecture

Early power-down digital memory device and method

Memory system with burst length shorter than prefetch length

Method and apparatus for controlling power states in a memory devic...

Mapping data masks in hardware by controller programming

Obtaining data mask mapping information

Write clock and data window tuning based on rank select

Device and method for maximizing performance on a memory interface...

Memory bus termination with memory unit having termination control

METHOD AND APPARATUS FOR INTEGRATING AND DETERMINING WHETHER A MEMO...

Method and apparatus for handling memory read return data from diff...

Dual-port buffer-to-memory interface

MULTI-TIER POINT-TO-POINT BUFFERED MEMORY INTERFACE