James W. Conary

Person

Beaverton, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory array leakage reduction circuit and method
- Patent number 7,345,947
- Issue date Mar 18, 2008
- Intel Corporation
- Jeffrey L. Miller
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array leakage reduction circuit and method
- Patent number 7,164,616
- Issue date Jan 16, 2007
- Intel Corporation
- Jeffrey L. Miller
- G11 - INFORMATION STORAGE
Information Patent Grant
Input buffer circuit with dual power down functions
- Patent number 6,330,679
- Issue date Dec 11, 2001
- Intel Corporation
- James Conary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Detecting states of signals
- Patent number 6,298,450
- Issue date Oct 2, 2001
- Intel Corporation
- Jonathan H. Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing timing variance of signals from an electronic device
- Patent number 6,175,928
- Issue date Jan 16, 2001
- Intel Corporation
- Jonathan H. Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to monitor a characteristic associated with an...
- Patent number 6,172,546
- Issue date Jan 9, 2001
- Intel Corporation
- Jonathan H. Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synchronous interface to a self-timed memory array
- Patent number 6,061,293
- Issue date May 9, 2000
- Intel Corporation
- Jeffrey Lee Miller
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for powering down an integrated circuit having...
- Patent number 5,935,253
- Issue date Aug 10, 1999
- Intel Corporation
- James W. Conary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit having a core which operates at a speed greater...
- Patent number 5,884,068
- Issue date Mar 16, 1999
- Intel Corporation
- James W. Conary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for powering down an integrated circuit transp...
- Patent number 5,842,029
- Issue date Nov 24, 1998
- Intel Corporation
- James W. Conary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for operating a microprocessor core and bus controller at...
- Patent number 5,634,117
- Issue date May 27, 1997
- Intel Corporation
- James W. Conary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for invalidating a cache while in a low power...
- Patent number 5,630,146
- Issue date May 13, 1997
- Intel Corporation
- James W. Conary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor with a core that operates at multiple frequencies
- Patent number 5,537,581
- Issue date Jul 16, 1996
- Intel Corporation
- James W. Conary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for invalidating a cache while in a low power...
- Patent number 5,481,731
- Issue date Jan 2, 1996
- Intel Corporation
- James W. Conary
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Memory array leakage reduction circuit and method
- Publication number 20070002673
- Publication date Jan 4, 2007
- Jeffrey L. Miller
- G11 - INFORMATION STORAGE
Information Patent Application
Memory array leakage reduction circuit and method
- Publication number 20060133185
- Publication date Jun 22, 2006
- Jeffrey L. Miller
- G11 - INFORMATION STORAGE

James W. Conary

Person

Patents Grantslast 30 patents

Memory array leakage reduction circuit and method

Memory array leakage reduction circuit and method

Input buffer circuit with dual power down functions

Detecting states of signals

Reducing timing variance of signals from an electronic device

Method and apparatus to monitor a characteristic associated with an...

Synchronous interface to a self-timed memory array

Method and apparatus for powering down an integrated circuit having...

Integrated circuit having a core which operates at a speed greater...

Method and apparatus for powering down an integrated circuit transp...

Apparatus for operating a microprocessor core and bus controller at...

Method and apparatus for invalidating a cache while in a low power...

Microprocessor with a core that operates at multiple frequencies

Method and apparatus for invalidating a cache while in a low power...

Patents Applicationslast 30 patents

Memory array leakage reduction circuit and method

Memory array leakage reduction circuit and method