James W. Dawson

Person

Poughkeepsie, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Digital voltage boost circuit
- Patent number 8,937,840
- Issue date Jan 20, 2015
- International Business Machines Corporation
- James W. Dawson
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for memory device precharging
- Patent number 8,472,271
- Issue date Jun 25, 2013
- International Business Machines Corporation
- James W. Dawson
- G11 - INFORMATION STORAGE
Information Patent Grant
ABIST data compression and serialization for memory built-in self t...
- Patent number 7,380,191
- Issue date May 27, 2008
- International Business Machines Corporation
- James W. Dawson
- G11 - INFORMATION STORAGE
Information Patent Grant
Clock control method and apparatus for a memory array
- Patent number 7,299,374
- Issue date Nov 20, 2007
- International Business Machines Corporation
- James W. Dawson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast pulse powered NOR decode apparatus for semiconductor devices
- Patent number 7,176,725
- Issue date Feb 13, 2007
- International Business Machines Corporation
- James W. Dawson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Fast pulse powered NOR decode apparatus with pulse stretching and r...
- Patent number 7,170,320
- Issue date Jan 30, 2007
- International Business Machines Corporation
- James W. Dawson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High density bitline selection apparatus for semiconductor memory d...
- Patent number 7,099,206
- Issue date Aug 29, 2006
- International Business Machines Corporation
- James W. Dawson
- G11 - INFORMATION STORAGE
Information Patent Grant
Global and local read control synchronization method and system for...
- Patent number 7,088,638
- Issue date Aug 8, 2006
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-binary address generation for ABIST
- Patent number 7,076,710
- Issue date Jul 11, 2006
- International Business Machines Corporation
- Thomas J. Knips
- G11 - INFORMATION STORAGE
Information Patent Grant
ABIST address generation
- Patent number 7,073,105
- Issue date Jul 4, 2006
- International Business Machines Corporation
- Thomas J. Knips
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for implementing multiple memory redundancy wi...
- Patent number 7,068,554
- Issue date Jun 27, 2006
- International Business Machines Corporation
- James W. Dawson
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for implementing multiple column redundancy fo...
- Patent number 7,064,990
- Issue date Jun 20, 2006
- International Business Machines Corporation
- James W. Dawson
- G11 - INFORMATION STORAGE
Information Patent Grant
SOI cell stability test method
- Patent number 6,728,912
- Issue date Apr 27, 2004
- International Business Machines Corporation
- James W. Dawson
- G11 - INFORMATION STORAGE
Information Patent Grant
Module level electronic redundancy
- Patent number 5,313,424
- Issue date May 17, 1994
- International Business Machines Corporation
- Robert D. Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Latch assisted fuse testing for customized integrated circuits
- Patent number 5,206,583
- Issue date Apr 27, 1993
- International Business Machines Corporation
- James W. Dawson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory cell and read circuit
- Patent number 4,995,001
- Issue date Feb 19, 1991
- International Business Machines Corporation
- James W. Dawson
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Digital Voltage Boost Circuit
- Publication number 20130155787
- Publication date Jun 20, 2013
- International Business Machines Corporation
- James W. Dawson
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEMS AND METHODS FOR MEMORY DEVICE PRECHARGING
- Publication number 20120213023
- Publication date Aug 23, 2012
- International Business Machines Corporation
- James W. Dawson
- G11 - INFORMATION STORAGE
Information Patent Application
CLOCK CONTROL METHOD AND APPARATUS FOR A MEMORY ARRAY
- Publication number 20080028255
- Publication date Jan 31, 2008
- International Business Machines Corporation
- James W. Dawson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method for SRAM decoding with single signal synchroni...
- Publication number 20060181950
- Publication date Aug 17, 2006
- International Business Machines Corporation
- John D. Davis
- G11 - INFORMATION STORAGE
Information Patent Application
Fast pulse powered NOR decode apparatus with pulse stretching and r...
- Publication number 20060176194
- Publication date Aug 10, 2006
- International Business Machines Corporation
- James W. Dawson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
GLOBAL AND LOCAL READ CONTROL SYNCHRONIZATION METHOD AND SYSTEM FOR...
- Publication number 20060176760
- Publication date Aug 10, 2006
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Application
ABIST data compression and serialization for memory built-in self t...
- Publication number 20060179377
- Publication date Aug 10, 2006
- International Business Machines Corporation
- James W. Dawson
- G11 - INFORMATION STORAGE
Information Patent Application
Fast pulse powered NOR decode apparatus for semiconductor devices
- Publication number 20060176081
- Publication date Aug 10, 2006
- International Business Machines Corporation
- James W. Dawson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Clock control method and apparatus for a memory array
- Publication number 20060174153
- Publication date Aug 3, 2006
- International Business Machines Corporation
- James W. Dawson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High density bitline selection apparatus for semiconductor memory d...
- Publication number 20060171215
- Publication date Aug 3, 2006
- International Business Machines Corporation
- James W. Dawson
- G11 - INFORMATION STORAGE
Information Patent Application
Non-binary address generation for ABIST
- Publication number 20040205435
- Publication date Oct 14, 2004
- International Business Machines Corporation
- Thomas J. Knips
- G11 - INFORMATION STORAGE
Information Patent Application
ABIST address generation
- Publication number 20040205405
- Publication date Oct 14, 2004
- International Business Machines Corporation
- Thomas J. Knips
- G11 - INFORMATION STORAGE
Information Patent Application
SOI cell stability test method
- Publication number 20020152434
- Publication date Oct 17, 2002
- International Business Machines Corporation
- James W. Dawson
- G11 - INFORMATION STORAGE

James W. Dawson

Person

Patents Grantslast 30 patents

Digital voltage boost circuit

Systems and methods for memory device precharging

ABIST data compression and serialization for memory built-in self t...

Clock control method and apparatus for a memory array

Fast pulse powered NOR decode apparatus for semiconductor devices

Fast pulse powered NOR decode apparatus with pulse stretching and r...

High density bitline selection apparatus for semiconductor memory d...

Global and local read control synchronization method and system for...

Non-binary address generation for ABIST

ABIST address generation

Apparatus and method for implementing multiple memory redundancy wi...

Method and apparatus for implementing multiple column redundancy fo...

SOI cell stability test method

Module level electronic redundancy

Latch assisted fuse testing for customized integrated circuits

Memory cell and read circuit

Patents Applicationslast 30 patents

Digital Voltage Boost Circuit

SYSTEMS AND METHODS FOR MEMORY DEVICE PRECHARGING

CLOCK CONTROL METHOD AND APPARATUS FOR A MEMORY ARRAY

Apparatus and method for SRAM decoding with single signal synchroni...

Fast pulse powered NOR decode apparatus with pulse stretching and r...

GLOBAL AND LOCAL READ CONTROL SYNCHRONIZATION METHOD AND SYSTEM FOR...

ABIST data compression and serialization for memory built-in self t...

Fast pulse powered NOR decode apparatus for semiconductor devices

Clock control method and apparatus for a memory array

High density bitline selection apparatus for semiconductor memory d...

Non-binary address generation for ABIST

ABIST address generation

SOI cell stability test method