James Yamaguchi

Person

Laguna Nigel, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Wire bond through-via structure and method
- Patent number 9,741,680
- Issue date Aug 22, 2017
- PFG IP LLC
- Randy Bindrup
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wire bond through-via structure and method
- Patent number 9,431,275
- Issue date Aug 30, 2016
- PFG IP LLC
- Randy Bindrup
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Anti-tamper wrapper interconnect method and a device
- Patent number 8,637,985
- Issue date Jan 28, 2014
- ISC8 Inc.
- Randy Bindrup
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method for defining an electrically conductive metal structure on a...
- Patent number 8,637,140
- Issue date Jan 28, 2014
- ISCS Inc.
- James Yamaguchi
- B32 - LAYERED PRODUCTS
Information Patent Grant
Method for fabricating a neo-layer using stud bumped bare die
- Patent number 8,609,473
- Issue date Dec 17, 2013
- ISC8 Inc.
- Peter Lieu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for precision integrated circuit die singulation using diffe...
- Patent number RE43877
- Issue date Dec 25, 2012
- Aprolase Development Co., LLC
- David Ludwig
- 438 - Semiconductor device manufacturing: process
Information Patent Grant
Stackable semiconductor chip layer comprising prefabricated trench...
- Patent number 7,786,562
- Issue date Aug 31, 2010
- Volkan Ozguz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for precision integrated circuit die singulation using diffe...
- Patent number 7,335,576
- Issue date Feb 26, 2008
- Irvine Sensors Corp.
- Ludwig David
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional module comprised of layers containing IC chips wi...
- Patent number 7,239,012
- Issue date Jul 3, 2007
- Irvine Sensors Corp.
- Angel Pepe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process of manufacturing multilayer modules
- Patent number 7,127,807
- Issue date Oct 31, 2006
- Irvine Sensors Corporation
- James Satsuo Yamaguchi
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method of making stackable layers containing encapsulated integrate...
- Patent number 6,797,537
- Issue date Sep 28, 2004
- Irvine Sensors Corporation
- Angel Antonio Pepe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stackable layers containing encapsulated integrated circuit chips w...
- Patent number 6,784,547
- Issue date Aug 31, 2004
- Irvine Sensors Corporation
- Angel Antonio Pepe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multilayer modules with flexible substrates
- Patent number 6,734,370
- Issue date May 11, 2004
- Irvine Sensors Corporation
- James Satsuo Yamaguchi
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Stacking of multilayer modules
- Patent number 6,717,061
- Issue date Apr 6, 2004
- Irvine Sensors Corporation
- James Satsuo Yamaguchi
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Stack of multilayer modules with heat-focusing metal layer
- Patent number 6,560,109
- Issue date May 6, 2003
- Irvine Sensors Corporation
- James Satsuo Yamaguchi
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Stackable layers containing encapsulated chips
- Patent number 6,117,704
- Issue date Sep 12, 2000
- Irvine Sensors Corporation
- James S. Yamaguchi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stack of equal layer neo-chips containing encapsulated IC chips of...
- Patent number 6,072,234
- Issue date Jun 6, 2000
- Irvine Sensors Corporation
- Andrew N Camien
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stackable layers containing encapsulated IC chips
- Patent number 5,953,588
- Issue date Sep 14, 1999
- Irvine Sensors Corporation
- Andrew N Camien
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR DEVICES FOR USE IN HIGH-PRESSURE ENVIRONMENTS
- Publication number 20240395934
- Publication date Nov 28, 2024
- The Boeing Company
- Leora Peltz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D-Stacked Module with Unlimited Scalable Memory Architecture for V...
- Publication number 20200006367
- Publication date Jan 2, 2020
- Irvine Sensors Corporation
- Christian Krutzik
- G11 - INFORMATION STORAGE
Information Patent Application
Method for Fabricating a Small Footprint Chip-Scale Package and a D...
- Publication number 20120211886
- Publication date Aug 23, 2012
- ISC8 Inc.
- Peter Lieu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Anti-Tamper Wrapper Interconnect Method and a Device
- Publication number 20120205801
- Publication date Aug 16, 2012
- Randy Bindrup
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Method for Defining an Electronically Conductive Metal Structure on...
- Publication number 20120094092
- Publication date Apr 19, 2012
- Irvine Sensors Corporation
- James Yamaguchi
- B32 - LAYERED PRODUCTS
Information Patent Application
Wire Bond Through-Via Structure and Method
- Publication number 20120068333
- Publication date Mar 22, 2012
- Irvine Sensors Corporation
- Randy Bindrup
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Fabricating a Neo-Layer Using Stud Bumped Bare Die
- Publication number 20120068336
- Publication date Mar 22, 2012
- Irvine Sensors Corporation
- Peter Lieu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Control of Solder Collapse in Stacked Microelectronic St...
- Publication number 20120069528
- Publication date Mar 22, 2012
- Irvine Sensors Corporation
- Randy Bindrup
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
Secure Anti-Tamper Integrated Layer Security Device Comprising Nano...
- Publication number 20110227603
- Publication date Sep 22, 2011
- Irvine Sensors Corporation
- John Leon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Tamper-resistant electronic circuit and module incorporating electr...
- Publication number 20110031982
- Publication date Feb 10, 2011
- Irvine Sensors Corporation
- John Leon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKABLE SEMICONDUCTOR CHIP LAYER COMPRISING PREFABRICATED TRENCH...
- Publication number 20100291735
- Publication date Nov 18, 2010
- Volkan Ozguz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for precision integrated circuit die singulation using diffe...
- Publication number 20060079072
- Publication date Apr 13, 2006
- Ludwig David
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Stackable semiconductor chip layer comprising prefabricated trench...
- Publication number 20050277288
- Publication date Dec 15, 2005
- Volkan Ozguz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Three-dimensional module comprised of layers containing IC chips wi...
- Publication number 20050037540
- Publication date Feb 17, 2005
- Angel Pepe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Stacked microelectronic module with vertical interconnect vias
- Publication number 20040113222
- Publication date Jun 17, 2004
- Volkan H. Ozguz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Multilayer modules with flexible substrates
- Publication number 20040040743
- Publication date Mar 4, 2004
- James Satsuo Yamaguchi
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Stackable layers containing encapsulated integrated circuit chips w...
- Publication number 20030127735
- Publication date Jul 10, 2003
- Angel Antonio Pepe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Stackable layers containing encapsulated integrated circuit chips w...
- Publication number 20030080419
- Publication date May 1, 2003
- Angel Antonio Pepe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Multilayer modules with flexible substrates
- Publication number 20030047353
- Publication date Mar 13, 2003
- James Satsuo Yamaguchi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACK OF MULTILAYER MODULES WITH HEAT-FOCUSSING METAL LAYER
- Publication number 20030048609
- Publication date Mar 13, 2003
- James Satsuo Yamaguchi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of manufacturing multilayer modules
- Publication number 20030049889
- Publication date Mar 13, 2003
- James Satsuo Yamaguchi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Stacking of multilayer modules
- Publication number 20030049424
- Publication date Mar 13, 2003
- James Satsuo Yamaguchi
- H01 - BASIC ELECTRIC ELEMENTS

James Yamaguchi

Person

Patents Grantslast 30 patents

Wire bond through-via structure and method

Wire bond through-via structure and method

Anti-tamper wrapper interconnect method and a device

Method for defining an electrically conductive metal structure on a...

Method for fabricating a neo-layer using stud bumped bare die

Method for precision integrated circuit die singulation using diffe...

Stackable semiconductor chip layer comprising prefabricated trench...

Method for precision integrated circuit die singulation using diffe...

Three-dimensional module comprised of layers containing IC chips wi...

Process of manufacturing multilayer modules

Method of making stackable layers containing encapsulated integrate...

Stackable layers containing encapsulated integrated circuit chips w...

Multilayer modules with flexible substrates

Stacking of multilayer modules

Stack of multilayer modules with heat-focusing metal layer

Stackable layers containing encapsulated chips

Stack of equal layer neo-chips containing encapsulated IC chips of...

Stackable layers containing encapsulated IC chips

Patents Applicationslast 30 patents

SEMICONDUCTOR DEVICES FOR USE IN HIGH-PRESSURE ENVIRONMENTS

3D-Stacked Module with Unlimited Scalable Memory Architecture for V...

Method for Fabricating a Small Footprint Chip-Scale Package and a D...

Anti-Tamper Wrapper Interconnect Method and a Device

Method for Defining an Electronically Conductive Metal Structure on...

Wire Bond Through-Via Structure and Method

Method for Fabricating a Neo-Layer Using Stud Bumped Bare Die

Method for Control of Solder Collapse in Stacked Microelectronic St...

Secure Anti-Tamper Integrated Layer Security Device Comprising Nano...

Tamper-resistant electronic circuit and module incorporating electr...

STACKABLE SEMICONDUCTOR CHIP LAYER COMPRISING PREFABRICATED TRENCH...

Method for precision integrated circuit die singulation using diffe...

Stackable semiconductor chip layer comprising prefabricated trench...

Three-dimensional module comprised of layers containing IC chips wi...

Stacked microelectronic module with vertical interconnect vias

Multilayer modules with flexible substrates

Stackable layers containing encapsulated integrated circuit chips w...

Stackable layers containing encapsulated integrated circuit chips w...

Multilayer modules with flexible substrates

STACK OF MULTILAYER MODULES WITH HEAT-FOCUSSING METAL LAYER

Method of manufacturing multilayer modules

Stacking of multilayer modules