Jan Paul van der Wagt

Person

Carlsbad, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Reducing timing skew in a circuit path
- Patent number 12,041,713
- Issue date Jul 16, 2024
- Teradyne, Inc.
- Jan Paul Antonie van der Wagt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for operating source synchronous devices
- Patent number 11,514,958
- Issue date Nov 29, 2022
- Teradyne, Inc.
- Ronald A. Sartschev
- G11 - INFORMATION STORAGE
Information Patent Grant
Parallel path delay line
- Patent number 11,283,436
- Issue date Mar 22, 2022
- Teradyne, Inc.
- Jan Paul Anthonie van der Wagt
- G01 - MEASURING TESTING
Information Patent Grant
Voltage driver circuit
- Patent number 11,119,155
- Issue date Sep 14, 2021
- Teradyne, Inc.
- Jan Paul Anthonie van der Wagt
- G01 - MEASURING TESTING
Information Patent Grant
Voltage driver with supply current stabilization
- Patent number 10,942,220
- Issue date Mar 9, 2021
- Teradyne, Inc.
- Jan Paul Anthonie van der Wagt
- G01 - MEASURING TESTING
Information Patent Grant
Voltage driver circuit calibration
- Patent number 10,761,130
- Issue date Sep 1, 2020
- Teradyne, Inc.
- Jan Paul Anthonie van der Wagt
- G01 - MEASURING TESTING
Information Patent Grant
Adjusting signal timing
- Patent number 10,276,229
- Issue date Apr 30, 2019
- Teradyne, Inc.
- Jan Paul Antonie van der Wagt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Deskew of rising and falling signal edges
- Patent number 9,503,065
- Issue date Nov 22, 2016
- Teradyne, Inc.
- Jan Paul Antonie van der Wagt
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method of reducing power consumption for audio playback
- Patent number 9,425,747
- Issue date Aug 23, 2016
- QUALCOMM Incorporated
- Seyfollah Bazarjani
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Edge generator-based phase locked loop reference clock generator fo...
- Patent number 9,397,670
- Issue date Jul 19, 2016
- Teradyne, Inc.
- Jan Paul Anthonie van der Wagt
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Automated test system with edge steering
- Patent number 9,279,857
- Issue date Mar 8, 2016
- Teradyne, Inc.
- Howard Lin
- G01 - MEASURING TESTING
Information Patent Grant
Edge triggered calibration
- Patent number 9,147,620
- Issue date Sep 29, 2015
- Teradyne, Inc.
- Jan Paul Anthonie van der Wagt
- G01 - MEASURING TESTING
Information Patent Grant
Buffer with active output impedance matching
- Patent number 8,410,824
- Issue date Apr 2, 2013
- Qualcomm, Incorporated
- Shahin Mehdizad Taleie
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Programmable gain circuit
- Patent number 7,868,681
- Issue date Jan 11, 2011
- Qualcomm, Incorporated
- Jan Paul van der Wagt
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Switches with passive bootstrap of control signal
- Patent number 7,728,650
- Issue date Jun 1, 2010
- QUALCOMM Incorporated
- Jan Paul van der Wagt
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
APPARATUS AND METHOD FOR OPERATING SOURCE SYNCHRONOUS DEVICES
- Publication number 20220044715
- Publication date Feb 10, 2022
- Teradyne, Inc.
- Ronald A. Sartschev
- G11 - INFORMATION STORAGE
Information Patent Application
VOLTAGE DRIVER CIRCUIT
- Publication number 20200341059
- Publication date Oct 29, 2020
- Teradyne, Inc.
- Jan Paul Anthonie van der Wagt
- G05 - CONTROLLING REGULATING
Information Patent Application
VOLTAGE DRIVER WITH SUPPLY CURRENT STABILIZATION
- Publication number 20200341060
- Publication date Oct 29, 2020
- Teradyne, Inc.
- Jan Paul Anthonie van der Wagt
- G05 - CONTROLLING REGULATING
Information Patent Application
PARALLEL PATH DELAY LINE
- Publication number 20200343882
- Publication date Oct 29, 2020
- Teradyne, Inc.
- Jan Paul Anthonie van der Wagt
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
REDUCING TIMING SKEW IN A CIRCUIT PATH
- Publication number 20190069394
- Publication date Feb 28, 2019
- Teradyne, Inc.
- Jan Paul Antonie van der Wagt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADJUSTING SIGNAL TIMING
- Publication number 20190066757
- Publication date Feb 28, 2019
- Teradyne, Inc.
- Jan Paul Antonie van der Wagt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Edge Generator-Based Phase Locked Loop Reference Clock Generator fo...
- Publication number 20160006441
- Publication date Jan 7, 2016
- Teradyne, Inc.
- Jan Paul Anthonie van der Wagt
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
AUTOMATED TEST SYSTEM WITH EDGE STEERING
- Publication number 20150137838
- Publication date May 21, 2015
- Teradyne, Inc.
- Howard Lin
- G01 - MEASURING TESTING
Information Patent Application
EDGE TRIGGERED CALIBRATION
- Publication number 20130260485
- Publication date Oct 3, 2013
- Teradyne, Inc.
- Jan Paul Anthonie van der Wagt
- G01 - MEASURING TESTING
Information Patent Application
BUFFER WITH ACTIVE OUTPUT IMPEDANCE MATCHING
- Publication number 20100295581
- Publication date Nov 25, 2010
- QUALCOMM Incorporated
- Shahin Mehdizad Taleie
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYSTEM AND METHOD OF REDUCING POWER CONSUMPTION FOR AUDIO PLAYBACK
- Publication number 20090220110
- Publication date Sep 3, 2009
- QUALCOMM Incorporated
- Seyfollah Bazarjani
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SWITCHES WITH PASSIVE BOOTSTRAP
- Publication number 20080309400
- Publication date Dec 18, 2008
- QUALCOMM Incorporated
- Jan Paul van der Wagt
- H03 - BASIC ELECTRONIC CIRCUITRY

Jan Paul van der Wagt

Person

Patents Grantslast 30 patents

Reducing timing skew in a circuit path

Apparatus and method for operating source synchronous devices

Parallel path delay line

Voltage driver circuit

Voltage driver with supply current stabilization

Voltage driver circuit calibration

Adjusting signal timing

Deskew of rising and falling signal edges

System and method of reducing power consumption for audio playback

Edge generator-based phase locked loop reference clock generator fo...

Automated test system with edge steering

Edge triggered calibration

Buffer with active output impedance matching

Programmable gain circuit

Switches with passive bootstrap of control signal

Patents Applicationslast 30 patents

APPARATUS AND METHOD FOR OPERATING SOURCE SYNCHRONOUS DEVICES

VOLTAGE DRIVER CIRCUIT

VOLTAGE DRIVER WITH SUPPLY CURRENT STABILIZATION

PARALLEL PATH DELAY LINE

REDUCING TIMING SKEW IN A CIRCUIT PATH

ADJUSTING SIGNAL TIMING

Edge Generator-Based Phase Locked Loop Reference Clock Generator fo...

AUTOMATED TEST SYSTEM WITH EDGE STEERING

EDGE TRIGGERED CALIBRATION

BUFFER WITH ACTIVE OUTPUT IMPEDANCE MATCHING

SYSTEM AND METHOD OF REDUCING POWER CONSUMPTION FOR AUDIO PLAYBACK

SWITCHES WITH PASSIVE BOOTSTRAP