Jasmeet S. Chawla

Person

Hillsboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method of forming high density, high shorting margin, and low capac...
- Patent number 11,380,617
- Issue date Jul 5, 2022
- Intel Corporation
- Christopher J. Jezewski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistors with metal source and drain contacts including a Heusle...
- Patent number 11,107,908
- Issue date Aug 31, 2021
- Intel Corporation
- Sasikanth Manipatruni
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Techniques for forming vias and other interconnects for integrated...
- Patent number 11,069,609
- Issue date Jul 20, 2021
- Intel Corporation
- Sasikanth Manipatruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor devices with metal contacts including crystalline alloys
- Patent number 11,056,593
- Issue date Jul 6, 2021
- Intel Corporation
- Sasikanth Manipatruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Maskless air gap to prevent via punch through
- Patent number 10,971,394
- Issue date Apr 6, 2021
- Intel Corporation
- Manish Chandhok
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Magneto-electric spin orbit (MESO) structures having functional oxi...
- Patent number 10,957,844
- Issue date Mar 23, 2021
- Intel Corporation
- Jasmeet S. Chawla
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Compliant layer for wafer to wafer bonding
- Patent number 10,707,186
- Issue date Jul 7, 2020
- Intel Corporation
- Mauro J. Kobrinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned via below subtractively patterned interconnect
- Patent number 10,546,772
- Issue date Jan 28, 2020
- Intel Corporation
- Manish Chandhok
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic conductive routes and methods of making the same
- Patent number 10,497,613
- Issue date Dec 3, 2019
- Intel Corporation
- Jasmeet S. Chawla
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Maskless air gap to prevent via punch through
- Patent number 10,256,141
- Issue date Apr 9, 2019
- Intel Corporation
- Manish Chandhok
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for creating alternate hardmask cap interconnect structure w...
- Patent number 10,109,583
- Issue date Oct 23, 2018
- Intel Corporation
- Robert L. Bristol
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and structure to contact tight pitch conductive layers with...
- Patent number 10,032,643
- Issue date Jul 24, 2018
- Intel Corporation
- Jasmeet S. Chawla
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming high density, high shorting margin, and low capac...
- Patent number 9,911,694
- Issue date Mar 6, 2018
- Intel Corporation
- Christopher J. Jezewski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Diagonal hardmasks for improved overlay in fabricating back end of...
- Patent number 9,548,269
- Issue date Jan 17, 2017
- Intel Corporation
- Alan M. Myers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming high density, high shorting margin, and low capac...
- Patent number 9,385,082
- Issue date Jul 5, 2016
- Intel Corporation
- Christopher J. Jezewski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for forming interconnect layers having tight pitch intercon...
- Patent number 9,379,010
- Issue date Jun 28, 2016
- Intel Corporation
- Christopher J. Jezewski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Diagonal hardmasks for improved overlay in fabricating back end of...
- Patent number 9,209,077
- Issue date Dec 8, 2015
- Intel Corporation
- Alan M. Myers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming high density, high shorting margin, and low capac...
- Patent number 9,054,164
- Issue date Jun 9, 2015
- Intel Corporation
- Christopher J. Jezewski
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
BACKSIDE CONTACT BASED DIE EDGE GUARD RINGS
- Publication number 20240421101
- Publication date Dec 19, 2024
- Intel Corporation
- Sunny CHUGH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT INTERCONNECT STRUCTURES WITH GRAPHENE CAP
- Publication number 20220415818
- Publication date Dec 29, 2022
- Intel Corporation
- Carl Naylor
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING HIGH DENSITY, HIGH SHORTING MARGIN, AND LOW CAPAC...
- Publication number 20220270964
- Publication date Aug 25, 2022
- Intel Corporation
- Christopher J. JEZEWSKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES FOR FORMING VIAS AND OTHER INTERCONNECTS FOR INTEGRATED...
- Publication number 20200279805
- Publication date Sep 3, 2020
- Intel Corporation
- Sasikanth MANIPATRUNI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICES WITH METAL CONTACTS INCLUDING CRYSTALLINE ALLOYS
- Publication number 20200152781
- Publication date May 14, 2020
- Intel Corporation
- Sasikanth Manipatruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MAGNETO-ELECTRIC SPIN ORBIT (MESO) STRUCTURES HAVING FUNCTIONAL OXI...
- Publication number 20190259935
- Publication date Aug 22, 2019
- Intel Corporation
- Jasmeet S. CHAWLA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MASKLESS AIR GAP TO PREVENT VIA PUNCH THROUGH
- Publication number 20190189500
- Publication date Jun 20, 2019
- Intel Corporation
- Manish CHANDHOK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTORS WITH METAL SOURCE AND DRAIN CONTACTS INCLUDING A HEUSLE...
- Publication number 20190181249
- Publication date Jun 13, 2019
- Intel Corporation
- SASIKANTH MANIPATRUNI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONDUCTIVE CONNECTORS HAVING A RUTHENIUM/ALUMINUM-CONTAINING LINER...
- Publication number 20190074217
- Publication date Mar 7, 2019
- Intel Corporation
- Christopher J. Jezewski
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
SELF-ALIGNED VIA BELOW SUBTRACTIVELY PATTERNED INTERCONNECT
- Publication number 20190035677
- Publication date Jan 31, 2019
- Intel Corporation
- Manish CHANDHOK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MASKLESS AIR GAP TO PREVENT VIA PUNCH THROUGH
- Publication number 20180204760
- Publication date Jul 19, 2018
- Intel Corporation
- Manish CHANDHOK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING HIGH DENSITY, HIGH SHORTING MARGIN, AND LOW CAPAC...
- Publication number 20180182702
- Publication date Jun 28, 2018
- Intel Corporation
- Christopher J. JEZEWSKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC CONDUCTIVE ROUTES AND METHODS OF MAKING THE SAME
- Publication number 20180082942
- Publication date Mar 22, 2018
- Intel Corporation
- Jasmeet S. Chawla
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND STRUCTURE TO CONTACT TIGHT PITCH CONDUCTIVE LAYERS WITH...
- Publication number 20170330761
- Publication date Nov 16, 2017
- Intel Corporation
- Jasmeet S. CHAWLA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NOVEL METHOD FOR CREATING ALTERNATE HARDMASK CAP INTERCONNECT STRUC...
- Publication number 20170263551
- Publication date Sep 14, 2017
- Intel Corporation
- ROBERT L. BRISTOL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING HIGH DENSITY, HIGH SHORTING MARGIN, AND LOW CAPAC...
- Publication number 20160315046
- Publication date Oct 27, 2016
- Intel Corporation
- Christopher J. JEZEWSKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIAGONAL HARDMASKS FOR IMPROVED OVERLAY IN FABRICATING BACK END OF...
- Publication number 20160126184
- Publication date May 5, 2016
- Alan M. Myers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING HIGH DENSITY, HIGH SHORTING MARGIN, AND LOW CAPAC...
- Publication number 20150243599
- Publication date Aug 27, 2015
- Intel Corporation
- Christopher J. JEZEWSKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FORMING INTERCONNECT LAYERS HAVING TIGHT PITCH INTERCON...
- Publication number 20150214094
- Publication date Jul 30, 2015
- Christopher J. Jezewski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIAGONAL HARDMASKS FOR IMPROVED OVERLAY IN FABRICATING BACK END OF...
- Publication number 20150179513
- Publication date Jun 25, 2015
- Alan M. Myers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING HIGH DENSITY, HIGH SHORTING MARGIN, AND LOW CAPAC...
- Publication number 20150179515
- Publication date Jun 25, 2015
- Christopher J. Jezewski
- H01 - BASIC ELECTRIC ELEMENTS

Jasmeet S. Chawla

Person

Patents Grantslast 30 patents

Method of forming high density, high shorting margin, and low capac...

Transistors with metal source and drain contacts including a Heusle...

Techniques for forming vias and other interconnects for integrated...

Semiconductor devices with metal contacts including crystalline alloys

Maskless air gap to prevent via punch through

Magneto-electric spin orbit (MESO) structures having functional oxi...

Compliant layer for wafer to wafer bonding

Self-aligned via below subtractively patterned interconnect

Microelectronic conductive routes and methods of making the same

Maskless air gap to prevent via punch through

Method for creating alternate hardmask cap interconnect structure w...

Method and structure to contact tight pitch conductive layers with...

Method of forming high density, high shorting margin, and low capac...

Diagonal hardmasks for improved overlay in fabricating back end of...

Method of forming high density, high shorting margin, and low capac...

Methods for forming interconnect layers having tight pitch intercon...

Diagonal hardmasks for improved overlay in fabricating back end of...

Method of forming high density, high shorting margin, and low capac...

Patents Applicationslast 30 patents

BACKSIDE CONTACT BASED DIE EDGE GUARD RINGS

INTEGRATED CIRCUIT INTERCONNECT STRUCTURES WITH GRAPHENE CAP

METHOD OF FORMING HIGH DENSITY, HIGH SHORTING MARGIN, AND LOW CAPAC...

TECHNIQUES FOR FORMING VIAS AND OTHER INTERCONNECTS FOR INTEGRATED...

SEMICONDUCTOR DEVICES WITH METAL CONTACTS INCLUDING CRYSTALLINE ALLOYS

MAGNETO-ELECTRIC SPIN ORBIT (MESO) STRUCTURES HAVING FUNCTIONAL OXI...

MASKLESS AIR GAP TO PREVENT VIA PUNCH THROUGH

TRANSISTORS WITH METAL SOURCE AND DRAIN CONTACTS INCLUDING A HEUSLE...

CONDUCTIVE CONNECTORS HAVING A RUTHENIUM/ALUMINUM-CONTAINING LINER...

SELF-ALIGNED VIA BELOW SUBTRACTIVELY PATTERNED INTERCONNECT

MASKLESS AIR GAP TO PREVENT VIA PUNCH THROUGH

METHOD OF FORMING HIGH DENSITY, HIGH SHORTING MARGIN, AND LOW CAPAC...

MICROELECTRONIC CONDUCTIVE ROUTES AND METHODS OF MAKING THE SAME

METHOD AND STRUCTURE TO CONTACT TIGHT PITCH CONDUCTIVE LAYERS WITH...

NOVEL METHOD FOR CREATING ALTERNATE HARDMASK CAP INTERCONNECT STRUC...

METHOD OF FORMING HIGH DENSITY, HIGH SHORTING MARGIN, AND LOW CAPAC...

DIAGONAL HARDMASKS FOR IMPROVED OVERLAY IN FABRICATING BACK END OF...

METHOD OF FORMING HIGH DENSITY, HIGH SHORTING MARGIN, AND LOW CAPAC...

METHODS FOR FORMING INTERCONNECT LAYERS HAVING TIGHT PITCH INTERCON...

DIAGONAL HARDMASKS FOR IMPROVED OVERLAY IN FABRICATING BACK END OF...

METHOD OF FORMING HIGH DENSITY, HIGH SHORTING MARGIN, AND LOW CAPAC...