Jason M. Norman

Person

So. Burlington, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Functional simulation redundancy reduction by state comparison and...
- Patent number 8,539,404
- Issue date Sep 17, 2013
- International Business Machines Corporation
- Jesse E. Craig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structure for hardware assisted bus state transition circuit using...
- Patent number 8,347,019
- Issue date Jan 1, 2013
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Critical path redundant logic for mitigation of hardware across chi...
- Patent number 7,898,286
- Issue date Mar 1, 2011
- International Business Machines Corporation
- Igor Arsovski
- G01 - MEASURING TESTING
Information Patent Grant
System and method for system-on-chip interconnect verification
- Patent number 7,865,789
- Issue date Jan 4, 2011
- International Business Machines Corporation
- Serafino Bueti
- G01 - MEASURING TESTING
Information Patent Grant
Transition balancing for noise reduction/Di/Dt reduction during des...
- Patent number 7,823,107
- Issue date Oct 26, 2010
- International Business Machines Corporation
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Assigning clock arrival time for noise reduction
- Patent number 7,743,270
- Issue date Jun 22, 2010
- International Business Machines Corporation
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transition balancing for noise reduction /Di/Dt reduction during de...
- Patent number 7,643,591
- Issue date Jan 5, 2010
- International Business Machines Corproation
- Igor Arsovski
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method of manufacturing integrated circuits using pre-made and pre-...
- Patent number 7,519,941
- Issue date Apr 14, 2009
- International Business Machines Corporation
- Serafino Bueti
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
System and method for system-on-chip interconnect verification
- Patent number 7,313,738
- Issue date Dec 25, 2007
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit design verification using checkpointing
- Patent number 7,308,663
- Issue date Dec 11, 2007
- International Business Machines Corporation
- Jesse E. Craig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fiber optic transmission lines on an SOC
- Patent number 7,286,770
- Issue date Oct 23, 2007
- International Business Machines Corporation
- Gary R. Doyle
- G02 - OPTICS
Information Patent Grant
Method and apparatus for monitoring integrated circuit temperature...
- Patent number 7,275,011
- Issue date Sep 25, 2007
- International Business Machines Corporation
- Serafino Bueti
- G01 - MEASURING TESTING
Information Patent Grant
Wireless communication system within a system on a chip
- Patent number 7,248,838
- Issue date Jul 24, 2007
- International Business Machines Corporation
- Kenneth J Goodnow
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Semiconductor device comprising a plurality of memory structures
- Patent number 7,139,881
- Issue date Nov 21, 2006
- International Business Machines Corporation
- Kenneth J. Goodnow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wireless communication system within a system on a chip
- Patent number 7,103,320
- Issue date Sep 5, 2006
- International Business Machines Corporation
- Kenneth J Goodnow
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Data acknowledgment using impedance mismatching
- Patent number 7,091,743
- Issue date Aug 15, 2006
- International Business Machines Corporation
- Michael J. Boudreaux
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for correcting timing signals in integrated circuits
- Patent number 7,085,993
- Issue date Aug 1, 2006
- International Business Machine Corporation
- Kenneth J. Goodnow
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Auto-linking of function logic state with testcase regression list
- Patent number 6,934,656
- Issue date Aug 23, 2005
- International Business Machines Corporation
- Jason Michael Norman
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
FUNCTIONAL SIMULATION REDUNDANCY REDUCTION BY STATE COMPARISON AND...
- Publication number 20130080983
- Publication date Mar 28, 2013
- International Business Machines Corporation
- Jesse E. Craig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Critical Path Redundant Logic for Mitigation of Hardware Across Chi...
- Publication number 20100201377
- Publication date Aug 12, 2010
- International Business Machines Corporation
- Igor ARSOVSKI
- G01 - MEASURING TESTING
Information Patent Application
UNIVERSAL PERIPHERAL PROCESSOR SYSTEM FOR SOC ENVIRONMENTS ON AN IN...
- Publication number 20090132732
- Publication date May 21, 2009
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRUCTURE FOR UNIVERSAL PERIPHERAL PROCESSOR SYSTEM FOR SOC ENVIRON...
- Publication number 20090132747
- Publication date May 21, 2009
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Transition Balancing For Noise Reduction/Di/Dt Reduction During Des...
- Publication number 20090106724
- Publication date Apr 23, 2009
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHIFTING INACTIVE CLOCK EDGE FOR NOISE REDUCTION
- Publication number 20090102529
- Publication date Apr 23, 2009
- International Business Machines Corporation
- Igor Arsovski
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DESIGN STRUCTURE FOR HARDWARE ASSISTED BUS STATE TRANSITION CIRCUIT...
- Publication number 20080282015
- Publication date Nov 13, 2008
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Executing Software Within Real-Time Hardware Constraints Using Func...
- Publication number 20080282072
- Publication date Nov 13, 2008
- Todd E. Leonard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRUCTURE FOR EXECUTING SOFTWARE WITHIN REAL-TIME HARDWARE CONSTRAI...
- Publication number 20080278195
- Publication date Nov 13, 2008
- International Business Machines Corporation
- Kenneth Goodnow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FIBER OPTIC TRANSMISSION LINES ON AN SOC
- Publication number 20080212977
- Publication date Sep 4, 2008
- Gary R. Doyle
- G02 - OPTICS
Information Patent Application
System and method for system-on-chip interconnect verification
- Publication number 20080215945
- Publication date Sep 4, 2008
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE ASSISTED BUS STATE TRANSITION USING CONTENT ADDRESSABLE ME...
- Publication number 20080183941
- Publication date Jul 31, 2008
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASSIGNING CLOCK ARRIVAL TIME FOR NOISE REDUCTION
- Publication number 20080065923
- Publication date Mar 13, 2008
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHIFTING INACTIVE CLOCK EDGE FOR NOISE REDUCTION
- Publication number 20080046772
- Publication date Feb 21, 2008
- International Business Machines Corporation
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSITION BALANCING FOR NOISE REDUCTION /di/dt REDUCTION DURING DE...
- Publication number 20080043890
- Publication date Feb 21, 2008
- Igor Arsovski
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD OF MANUFACTURING INTEGRATED CIRCUITS USING PRE-MADE AND PRE-...
- Publication number 20070245290
- Publication date Oct 18, 2007
- Serafino Bueti
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
METHOD AND APPARATUS FOR RESOURCE-BASED THREAD ALLOCATION IN A MULT...
- Publication number 20070101332
- Publication date May 3, 2007
- International Business Machines Corporation
- Adam Joseph Courchesne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT DESIGN VERIFICATION USING CHECKPOINTING
- Publication number 20070074135
- Publication date Mar 29, 2007
- International Business Machines Corporation
- Jesse E. Craig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR MONITORING INTEGRATED CIRCUIT TEMPERATURE...
- Publication number 20070005290
- Publication date Jan 4, 2007
- International Business Machines Corporation
- Serafino Bueti
- G01 - MEASURING TESTING
Information Patent Application
A METHOD AND APPARATUS FOR TRANSFERRING DATA BETWEEN CORES IN AN IN...
- Publication number 20060262779
- Publication date Nov 23, 2006
- International Business Machines Corporation
- Adam J. Courchesne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR SYSTEM-ON-CHIP INTERCONNECT VERIFICATION
- Publication number 20060242524
- Publication date Oct 26, 2006
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Wireless communication system within a system on a chip
- Publication number 20060189294
- Publication date Aug 24, 2006
- International Business Machines Corporation
- Kenneth J. Goodnow
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD AND APPARATUS FOR SERVICING THREADS WITHIN A MULTI-PROCESSOR...
- Publication number 20060095905
- Publication date May 4, 2006
- International Business Machines Corporation
- Adam J. Courchesne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR ARBITRATION BETWEEN SHARED PERIPHERAL CORE DE...
- Publication number 20060041705
- Publication date Feb 23, 2006
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTO-LINKING OF FUNCTION LOGIC STATE WITH TESTCASE REGRESSION LIST
- Publication number 20050096862
- Publication date May 5, 2005
- International Business Machines Corporation
- Jason Michael Norman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Data acknowledgment using impedance mismatching
- Publication number 20050076170
- Publication date Apr 7, 2005
- International Business Machines Corporation
- Michael J. Boudreaux
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DEVICE COMPRISING A PLURALITY OF MEMORY STRUCTURES
- Publication number 20050071575
- Publication date Mar 31, 2005
- International Business Machines Corporation
- Kenneth J. Goodnow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FIBER OPTIC TRANSMISSION LINES ON AN SOC
- Publication number 20050013527
- Publication date Jan 20, 2005
- International Business Machines Corporation
- Gary R. Doyle
- G02 - OPTICS
Information Patent Application
WIRELESS COMMUNICATION SYSTEM WITHIN A SYSTEM ON A CHIP
- Publication number 20040209575
- Publication date Oct 21, 2004
- International Business Machines Corporation
- Kenneth J. Goodnow
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
System and method for correcting timing signals in integrated circuits
- Publication number 20040019844
- Publication date Jan 29, 2004
- International Business Machines Corporation
- Kenneth J. Goodnow
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Jason M. Norman

Person

Patents Grantslast 30 patents

Functional simulation redundancy reduction by state comparison and...

Structure for hardware assisted bus state transition circuit using...

Critical path redundant logic for mitigation of hardware across chi...

System and method for system-on-chip interconnect verification

Transition balancing for noise reduction/Di/Dt reduction during des...

Assigning clock arrival time for noise reduction

Transition balancing for noise reduction /Di/Dt reduction during de...

Method of manufacturing integrated circuits using pre-made and pre-...

System and method for system-on-chip interconnect verification

Circuit design verification using checkpointing

Fiber optic transmission lines on an SOC

Method and apparatus for monitoring integrated circuit temperature...

Wireless communication system within a system on a chip

Semiconductor device comprising a plurality of memory structures

Wireless communication system within a system on a chip

Data acknowledgment using impedance mismatching

System and method for correcting timing signals in integrated circuits

Auto-linking of function logic state with testcase regression list

Patents Applicationslast 30 patents

FUNCTIONAL SIMULATION REDUNDANCY REDUCTION BY STATE COMPARISON AND...

Critical Path Redundant Logic for Mitigation of Hardware Across Chi...

UNIVERSAL PERIPHERAL PROCESSOR SYSTEM FOR SOC ENVIRONMENTS ON AN IN...

STRUCTURE FOR UNIVERSAL PERIPHERAL PROCESSOR SYSTEM FOR SOC ENVIRON...

Transition Balancing For Noise Reduction/Di/Dt Reduction During Des...

SHIFTING INACTIVE CLOCK EDGE FOR NOISE REDUCTION

DESIGN STRUCTURE FOR HARDWARE ASSISTED BUS STATE TRANSITION CIRCUIT...

Executing Software Within Real-Time Hardware Constraints Using Func...

STRUCTURE FOR EXECUTING SOFTWARE WITHIN REAL-TIME HARDWARE CONSTRAI...

FIBER OPTIC TRANSMISSION LINES ON AN SOC

System and method for system-on-chip interconnect verification

HARDWARE ASSISTED BUS STATE TRANSITION USING CONTENT ADDRESSABLE ME...

ASSIGNING CLOCK ARRIVAL TIME FOR NOISE REDUCTION

SHIFTING INACTIVE CLOCK EDGE FOR NOISE REDUCTION

TRANSITION BALANCING FOR NOISE REDUCTION /di/dt REDUCTION DURING DE...

METHOD OF MANUFACTURING INTEGRATED CIRCUITS USING PRE-MADE AND PRE-...

METHOD AND APPARATUS FOR RESOURCE-BASED THREAD ALLOCATION IN A MULT...

CIRCUIT DESIGN VERIFICATION USING CHECKPOINTING

METHOD AND APPARATUS FOR MONITORING INTEGRATED CIRCUIT TEMPERATURE...

A METHOD AND APPARATUS FOR TRANSFERRING DATA BETWEEN CORES IN AN IN...

SYSTEM AND METHOD FOR SYSTEM-ON-CHIP INTERCONNECT VERIFICATION

Wireless communication system within a system on a chip

METHOD AND APPARATUS FOR SERVICING THREADS WITHIN A MULTI-PROCESSOR...

SYSTEM AND METHOD FOR ARBITRATION BETWEEN SHARED PERIPHERAL CORE DE...

AUTO-LINKING OF FUNCTION LOGIC STATE WITH TESTCASE REGRESSION LIST

Data acknowledgment using impedance mismatching

SEMICONDUCTOR DEVICE COMPRISING A PLURALITY OF MEMORY STRUCTURES

FIBER OPTIC TRANSMISSION LINES ON AN SOC

WIRELESS COMMUNICATION SYSTEM WITHIN A SYSTEM ON A CHIP

System and method for correcting timing signals in integrated circuits