Javier Soto Gonzalez

Person

Phoenix, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Sacrificial pads to prevent galvanic corrosion of FLI bumps in EMIB...
- Patent number 12,068,172
- Issue date Aug 20, 2024
- Intel Corporation
- Tarek A. Ibrahim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High performance integrated RF passives using dual lithography process
- Patent number 12,002,745
- Issue date Jun 4, 2024
- Intel Corporation
- Adel A. Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor packaging with high density interconnects
- Patent number 11,881,457
- Issue date Jan 23, 2024
- Tahoe Research, LTD.
- Adel A. Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Panel level packaging for multi-die products interconnected with ve...
- Patent number 11,735,531
- Issue date Aug 22, 2023
- Intel Corporation
- Srinivas V. Pietambaram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package substrate with high-density interconnect layer having pilla...
- Patent number 11,532,584
- Issue date Dec 20, 2022
- Intel Corporation
- Robert Alan May
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High performance integrated RF passives using dual lithography process
- Patent number 11,227,825
- Issue date Jan 18, 2022
- Intel Corporation
- Adel A. Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Panel level packaging for multi-die products interconnected with ve...
- Patent number 11,101,222
- Issue date Aug 24, 2021
- Intel Corporation
- Srinivas V. Pietambaram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Scalable embedded silicon bridge via pillars in lithographically de...
- Patent number 11,004,824
- Issue date May 11, 2021
- Intel Corporation
- Adel A. Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Die interconnect substrate, an electrical device, and a method for...
- Patent number 10,978,399
- Issue date Apr 13, 2021
- Intel Corporation
- Kristof Darmawikarta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package power delivery using plane and shaped vias
- Patent number 10,971,416
- Issue date Apr 6, 2021
- Intel Corporation
- Krishna Bharath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor packaging with high density interconnects
- Patent number 10,971,453
- Issue date Apr 6, 2021
- Intel Corporation
- Adel A. Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package substrate with high-density interconnect layer having pilla...
- Patent number 10,872,872
- Issue date Dec 22, 2020
- Intel Corporation
- Robert Alan May
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making a flexible wearable circuit
- Patent number 10,798,817
- Issue date Oct 6, 2020
- Intel Corporation
- Aleksandar Aleksov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package power delivery using plane and shaped vias
- Patent number 10,410,939
- Issue date Sep 10, 2019
- Intel Corporation
- Krishna Bharath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stretchable electronic assembly
- Patent number 10,327,330
- Issue date Jun 18, 2019
- Intel Corporation
- Aleksandar Aleksov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bendable and stretchable electronic devices and methods
- Patent number 10,204,855
- Issue date Feb 12, 2019
- Intel Corporation
- Alejandro Levander
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Panel level fabrication of package substrates with integrated stiff...
- Patent number 9,832,860
- Issue date Nov 28, 2017
- Intel Corporation
- Robert Starkston
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with embedded die and its methods of fabrication
- Patent number 9,780,054
- Issue date Oct 3, 2017
- Intel Corporation
- John S. Guzek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pad-less interconnect for electrical coreless substrate
- Patent number 9,691,727
- Issue date Jun 27, 2017
- Intel Corporation
- Javier Soto Gonzalez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming sensor integrated packages and structures formed...
- Patent number 9,505,607
- Issue date Nov 29, 2016
- Intel Corporation
- Kyu Oh Lee
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Forming die backside coating structures with coreless packages
- Patent number 9,165,914
- Issue date Oct 20, 2015
- Intel Corporation
- Rahul N. Manepalli
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
PANEL LEVEL PACKAGING FOR MULTI-DIE PRODUCTS INTERCONNECTED WITH VE...
- Publication number 20230326866
- Publication date Oct 12, 2023
- Intel Corporation
- Srinivas V. PIETAMBARAM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH PERFORMANCE INTEGRATED RF PASSIVES USING DUAL LITHOGRAPHY PROCESS
- Publication number 20220102261
- Publication date Mar 31, 2022
- Intel Corporation
- Adel A. ELSHERBINI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PANEL LEVEL PACKAGING FOR MULTI-DIE PRODUCTS INTERCONNECTED WITH VE...
- Publication number 20210343653
- Publication date Nov 4, 2021
- Intel Corporation
- Srinivas V. PIETAMBARAM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SCALABLE EMBEDDED SILICON BRIDGE VIA PILLARS IN LITHOGRAPHICALLY DE...
- Publication number 20210225807
- Publication date Jul 22, 2021
- Intel Corporation
- Adel A. Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGING WITH HIGH DENSITY INTERCONNECTS
- Publication number 20210193583
- Publication date Jun 24, 2021
- Intel Corporation
- Adel A. Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE SUBSTRATE WITH HIGH-DENSITY INTERCONNECT LAYER HAVING PILLA...
- Publication number 20210066232
- Publication date Mar 4, 2021
- Intel Corporation
- Robert Alan MAY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SACRIFICIAL PADS TO PREVENT GALVANIC CORROSION OF FLI BUMPS IN EMIB...
- Publication number 20210035818
- Publication date Feb 4, 2021
- Intel Corporation
- Tarek A. IBRAHIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Die Interconnect Substrate, an Electrical Device, and a Method for...
- Publication number 20200051915
- Publication date Feb 13, 2020
- Intel Corporation
- Kristof Darmawikarta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE SUBSTRATE WITH HIGH-DENSITY INTERCONNECT LAYER HAVING PILLA...
- Publication number 20190363063
- Publication date Nov 28, 2019
- Intel Corporation
- Robert Alan MAY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE POWER DELIVERY USING PLANE AND SHAPED VIAS
- Publication number 20190355636
- Publication date Nov 21, 2019
- Intel Corporation
- Krishna BHARATH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGING WITH HIGH DENSITY INTERCONNECTS
- Publication number 20190259705
- Publication date Aug 22, 2019
- Intel Corporation
- Adel A. Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PANEL LEVEL PACKAGING FOR MULTI-DIE PRODUCTS INTERCONNECTED WITH VE...
- Publication number 20190189563
- Publication date Jun 20, 2019
- Intel Corporation
- Srinivas V. PIETAMBARAM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IMPROVED PACKAGE POWER DELIVERY USING PLANE AND SHAPED VIAS
- Publication number 20180331003
- Publication date Nov 15, 2018
- Intel Corporation
- Krishna BHARATH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH PERFORMANCE INTEGRATED RF PASSIVES USING DUAL LITHOGRAPHY PROCESS
- Publication number 20180315690
- Publication date Nov 1, 2018
- Intel Corporation
- Adel A. ELSHERBINI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRETCHABLE ELECTRONIC ASSEMBLY
- Publication number 20180295720
- Publication date Oct 11, 2018
- Intel Corporation
- Aleksandar Aleksov
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
SCALABLE EMBEDDED SILICON BRIDGE VIA PILLARS IN LITHOGRAPHICALLY DE...
- Publication number 20180182707
- Publication date Jun 28, 2018
- Intel Corporation
- Adel A. Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURAL BRACE FOR ELECTRONIC CIRCUIT WITH STRETCHABLE SUBSTRATE
- Publication number 20170344055
- Publication date Nov 30, 2017
- Intel Corporation
- Aleksandar Aleksov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS OF FORMING SENSOR INTEGRATED PACKAGES AND STRUCTURES FORMED...
- Publication number 20160280535
- Publication date Sep 29, 2016
- Intel Corporation
- Kyu Oh Lee
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
BENDABLE AND STRETCHABLE ELECTRONIC DEVICES AND METHODS
- Publication number 20160284630
- Publication date Sep 29, 2016
- Intel Corporation
- Alejandro Levander
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PANEL LEVEL FABRICATION OF PACKAGE SUBSTRATES WITH INTEGRATED STIFF...
- Publication number 20160095209
- Publication date Mar 31, 2016
- Intel Corporation
- Robert STARKSTON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESSES OF MAKING PAD-LESS INTERCONNECT FOR ELECTRICAL CORELESS S...
- Publication number 20150221608
- Publication date Aug 6, 2015
- Intel Corporation
- Javier SOTO GONZALEZ
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE WITH EMBEDDED DIE AND ITS METHODS OF FABRICATION
- Publication number 20150050781
- Publication date Feb 19, 2015
- lintel Corporation
- John S. Guzek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMING DIE BACKSIDE COATING STRUCTURES WITH CORELESS PACKAGES
- Publication number 20130252376
- Publication date Sep 26, 2013
- Rahul N. Manepalli
- H01 - BASIC ELECTRIC ELEMENTS

Javier Soto Gonzalez

Person

Patents Grantslast 30 patents

Sacrificial pads to prevent galvanic corrosion of FLI bumps in EMIB...

High performance integrated RF passives using dual lithography process

Semiconductor packaging with high density interconnects

Panel level packaging for multi-die products interconnected with ve...

Package substrate with high-density interconnect layer having pilla...

High performance integrated RF passives using dual lithography process

Panel level packaging for multi-die products interconnected with ve...

Scalable embedded silicon bridge via pillars in lithographically de...

Die interconnect substrate, an electrical device, and a method for...

Package power delivery using plane and shaped vias

Semiconductor packaging with high density interconnects

Package substrate with high-density interconnect layer having pilla...

Method for making a flexible wearable circuit

Package power delivery using plane and shaped vias

Stretchable electronic assembly

Bendable and stretchable electronic devices and methods

Panel level fabrication of package substrates with integrated stiff...

Semiconductor package with embedded die and its methods of fabrication

Pad-less interconnect for electrical coreless substrate

Methods of forming sensor integrated packages and structures formed...

Forming die backside coating structures with coreless packages

Patents Applicationslast 30 patents

PANEL LEVEL PACKAGING FOR MULTI-DIE PRODUCTS INTERCONNECTED WITH VE...

HIGH PERFORMANCE INTEGRATED RF PASSIVES USING DUAL LITHOGRAPHY PROCESS

PANEL LEVEL PACKAGING FOR MULTI-DIE PRODUCTS INTERCONNECTED WITH VE...

SCALABLE EMBEDDED SILICON BRIDGE VIA PILLARS IN LITHOGRAPHICALLY DE...

SEMICONDUCTOR PACKAGING WITH HIGH DENSITY INTERCONNECTS

PACKAGE SUBSTRATE WITH HIGH-DENSITY INTERCONNECT LAYER HAVING PILLA...

SACRIFICIAL PADS TO PREVENT GALVANIC CORROSION OF FLI BUMPS IN EMIB...

Die Interconnect Substrate, an Electrical Device, and a Method for...

PACKAGE SUBSTRATE WITH HIGH-DENSITY INTERCONNECT LAYER HAVING PILLA...

PACKAGE POWER DELIVERY USING PLANE AND SHAPED VIAS

SEMICONDUCTOR PACKAGING WITH HIGH DENSITY INTERCONNECTS

PANEL LEVEL PACKAGING FOR MULTI-DIE PRODUCTS INTERCONNECTED WITH VE...

IMPROVED PACKAGE POWER DELIVERY USING PLANE AND SHAPED VIAS

HIGH PERFORMANCE INTEGRATED RF PASSIVES USING DUAL LITHOGRAPHY PROCESS

STRETCHABLE ELECTRONIC ASSEMBLY

SCALABLE EMBEDDED SILICON BRIDGE VIA PILLARS IN LITHOGRAPHICALLY DE...

STRUCTURAL BRACE FOR ELECTRONIC CIRCUIT WITH STRETCHABLE SUBSTRATE

METHODS OF FORMING SENSOR INTEGRATED PACKAGES AND STRUCTURES FORMED...

BENDABLE AND STRETCHABLE ELECTRONIC DEVICES AND METHODS

PANEL LEVEL FABRICATION OF PACKAGE SUBSTRATES WITH INTEGRATED STIFF...

PROCESSES OF MAKING PAD-LESS INTERCONNECT FOR ELECTRICAL CORELESS S...

SEMICONDUCTOR PACKAGE WITH EMBEDDED DIE AND ITS METHODS OF FABRICATION

FORMING DIE BACKSIDE COATING STRUCTURES WITH CORELESS PACKAGES