Jay Thomas Young

Person

Louisville, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Configurable logic block (CLB) internal routing architecture for en...
- Patent number 10,715,149
- Issue date Jul 14, 2020
- Xilinx, Inc.
- Eric F. Dellinger
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method of selecting routing resources in a multi-chip integrated ci...
- Patent number 10,467,373
- Issue date Nov 5, 2019
- Jay T. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods of prioritizing routing resources to generate and evaluate...
- Patent number 8,418,221
- Issue date Apr 9, 2013
- Xilinx, Inc.
- Jay T. Young
- G01 - MEASURING TESTING
Information Patent Grant
Generating a module interface for partial reconfiguration design flows
- Patent number 8,332,788
- Issue date Dec 11, 2012
- Xilinx, Inc.
- Jay T. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generating a module interface for partial reconfiguration design flows
- Patent number 7,941,777
- Issue date May 10, 2011
- Xilinx, Inc.
- Jay T. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for providing secure intellectual property cor...
- Patent number 7,890,917
- Issue date Feb 15, 2011
- Xilinx, Inc.
- Jay T. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for generating an area constraint for a module...
- Patent number 7,673,272
- Issue date Mar 2, 2010
- Xilinx, Inc.
- Jay T. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for modular circuit design for a programmable...
- Patent number 7,600,210
- Issue date Oct 6, 2009
- Xilinx, Inc.
- Jeffrey M. Mason
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Design methodology to support relocatable bit streams for dynamic p...
- Patent number 7,509,617
- Issue date Mar 24, 2009
- Xilinx, Inc.
- Jay T. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for reducing the number of test designs for de...
- Patent number 7,480,842
- Issue date Jan 20, 2009
- Xilinx, Inc.
- Jay T. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing design execution run time bit stream size for device testing
- Patent number 7,299,430
- Issue date Nov 20, 2007
- Xilinx, Inc.
- Ian L. McEwen
- G01 - MEASURING TESTING
Information Patent Grant
Methods of routing programmable logic devices to minimize programmi...
- Patent number 7,249,335
- Issue date Jul 24, 2007
- Xilinx, Inc.
- Jay T. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing with frame awareness to minimize device programming time an...
- Patent number 7,149,997
- Issue date Dec 12, 2006
- Xilinx, Inc.
- Jay T. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods of routing programmable logic devices to minimize programmi...
- Patent number 7,143,384
- Issue date Nov 28, 2006
- Xilinx, Inc.
- Jay T. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods of generating test designs for testing specific routing res...
- Patent number 7,058,919
- Issue date Jun 6, 2006
- Xilinx, Inc.
- Jay T. Young
- G01 - MEASURING TESTING
Information Patent Grant
Methods of resource optimization in programmable logic devices to r...
- Patent number 6,944,809
- Issue date Sep 13, 2005
- Xilinx, Inc.
- Andrew W. Lai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dedicated resource placement enhancement
- Patent number 6,760,899
- Issue date Jul 6, 2004
- Xilinx, Inc.
- Jay T. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Frequency driven layout and method for field programmable gate arrays
- Patent number 5,659,484
- Issue date Aug 19, 1997
- Xilinx, Inc.
- David Wayne Bennett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Frequency driven layout system and method for field programmable ga...
- Patent number 5,648,913
- Issue date Jul 15, 1997
- Xilinx, Inc.
- David Wayne Bennett
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
U-TURN CIRCUITRY TO CONVERT INTER-LAYER CONNECTIONS OF AN INTEGRATE...
- Publication number 20240194645
- Publication date Jun 13, 2024
- Xilinx, Inc.
- Jay T. YOUNG
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD OF SELECTING ROUTING RESOURCES IN A MULTI-CHIP INTEGRATED CI...
- Publication number 20190258767
- Publication date Aug 22, 2019
- Xilinx, Inc.
- Jay T. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods of resource optimization in programmable logic devices to r...
- Publication number 20040030975
- Publication date Feb 12, 2004
- Xilinx, Inc.
- Andrew W. Lai
- G06 - COMPUTING CALCULATING COUNTING

Jay Thomas Young

Person

Patents Grantslast 30 patents

Configurable logic block (CLB) internal routing architecture for en...

Method of selecting routing resources in a multi-chip integrated ci...

Methods of prioritizing routing resources to generate and evaluate...

Generating a module interface for partial reconfiguration design flows

Generating a module interface for partial reconfiguration design flows

Method and apparatus for providing secure intellectual property cor...

Method and apparatus for generating an area constraint for a module...

Method and apparatus for modular circuit design for a programmable...

Design methodology to support relocatable bit streams for dynamic p...

Method and apparatus for reducing the number of test designs for de...

Reducing design execution run time bit stream size for device testing

Methods of routing programmable logic devices to minimize programmi...

Routing with frame awareness to minimize device programming time an...

Methods of routing programmable logic devices to minimize programmi...

Methods of generating test designs for testing specific routing res...

Methods of resource optimization in programmable logic devices to r...

Dedicated resource placement enhancement

Frequency driven layout and method for field programmable gate arrays

Frequency driven layout system and method for field programmable ga...

Patents Applicationslast 30 patents

U-TURN CIRCUITRY TO CONVERT INTER-LAYER CONNECTIONS OF AN INTEGRATE...

METHOD OF SELECTING ROUTING RESOURCES IN A MULTI-CHIP INTEGRATED CI...

Methods of resource optimization in programmable logic devices to r...