Jayprakash Chipalkatti

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Cupertino, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
IC package design and methodology to compensate for die-substrate C...
- Patent number 11,495,568
- Issue date Nov 8, 2022
- NVIDIA Corporation
- Jayprakash Chipalkatti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
IC package design and methodology to compensate for die-substrate C...
- Patent number 10,943,882
- Issue date Mar 9, 2021
- NVIDIA Corporation
- Jayprakash Chipalkatti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thermal performance of logic chip in a package-on-package structure
- Patent number 10,096,534
- Issue date Oct 9, 2018
- NVIDIA Corporation
- Abraham F. Yee
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
IC PACKAGE DESIGN AND METHODOLOGY TO COMPENSATE FOR DIE-SUBSTRATE C...
- Publication number 20210151403
- Publication date May 20, 2021
- NVIDIA Corporation
- Jayprakash Chipalkatti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IC PACKAGE DESIGN AND METHODOLOGY TO COMPENSATE FOR DIE-SUBSTRATE C...
- Publication number 20210066227
- Publication date Mar 4, 2021
- NVIDIA Corporation
- Jayprakash Chipalkatti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THERMAL PERFORMANCE OF LOGIC CHIP IN A PACKAGE-ON-PACKAGE STRUCTURE
- Publication number 20140131847
- Publication date May 15, 2014
- NVIDIA Corporation
- Abraham F. Yee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF EMBEDDING CPU/GPU/LOGIC CHIP INTO A SUBSTRATE OF A PACKAG...
- Publication number 20140133105
- Publication date May 15, 2014
- NVIDIA Corporation
- Abraham F. Yee
- H01 - BASIC ELECTRIC ELEMENTS