Patent Application
20140133105
1. Field of the Invention
Embodiments of the present invention generally relate to integrated circuit chip packaging and, more specifically, to a package-on-package (POP) packaging system with a high power chip and a low power chip.
2. Description of the Related Art
With the development of the electronics industry, there are increasing demands for smaller electronic devices with improved performance. In order to achieve a higher integration density and a smaller footprint of electronic components, a so-called “package-on-package (POP)” technology has been developed. POP is a three-dimensional packaging technology used to vertically stack a plurality of leadframe-based semiconductor packages atop each other with an interface to route signals between them.
Minimizing the thickness of the package has been a challenge to the successful implementation of the POP technology since there is generally a trade-off between the thermal management of chips and other devices contained in the package and the performance of the devices. Specifically, by locating memory chips, passive devices, and other low-power components of an IC package as close as possible to the central processor unit (CPU) and other high-power devices in an IC package, communication between devices in the IC package is accelerated and packaging parasitics are reduced. However, heat generated by higher-power chips is known to adversely affect memory chips and other devices positioned nearby. Consequently, it is not thermally feasible to stack memory chips and passive devices directly on or under a CPU or other high-power chip when incorporated into a single IC package, since such a configuration necessarily limits the power of the high-power chip or affects the performance of the memory chips.
As the foregoing illustrates, there is a need in the art for a package system having a greater density of integrated circuits with a corresponding reduction in package size. There is a further need for a high-power chip and a low-power chip arrangement in a vertical stack which prevents heat transfer between the chips.
Embodiments of the present invention set forth an IC system in which one or more low-power chips can be positioned proximate high-power chips without suffering the effects of overheating. In one embodiment, the IC system includes a high-power chip embedded in a first packaging substrate, and a low-power chip disposed on a second packaging substrate which is positioned above the first packaging substrate to form a stack. Because portions of the first packaging substrate thermally insulate the embedded high-power chip from the low-power chip, the low-power chip can be positioned proximate the high-power chip without being overheated. In certain embodiments, a thin heat distribution layer is positioned adjacent to a side of the high-power chip to spread heat of the high-power chip into the first packaging substrate. In a molded POP packaging system, heat in the first packaging substrate is transferred through solder balls into an underlying printed circuit board (PCB), which serves as a heat sink for the IC system.
One advantage of the present invention is that a memory chip or other low-power chip can be positioned in close proximity to a high-power chip that is embedded in a packaging substrate in the same IC system without being overheated by the high-power chip. Such close proximity advantageously reduces the overall thickness of the packaging system, thus a thinner and lighter electronic device is realized. By having a heat distribution layer disposed adjacent to the high-power chip, the heat generated by the high-power chip can be effectively dissipated into the printed circuit board (PCB), which further prevents heat transfer from the high-power chip to the low-power chip. Therefore, the lifetime of the low-power chip is extended.
So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
For clarity, identical reference numbers have been used, where applicable, to designate identical elements that are common between figures. It is contemplated that features of one embodiment may be incorporated in other embodiments without further recitation.
In this disclosure, high-power chip 101 is a high-power processor, such as a central processing unit (CPU), a graphics processing unit (GPU), application processor or other logic device, or any IC chip capable of generating enough heat during operation to adversely affect the performance of low-power chip 101 or passive devices located in the IC system 100. For example, a high-power chip is typically one that generates at least 10 W of heat or more during normal operation. Conversely, a low-power chip is one that does not generate enough heat during operation to adversely affect the performance of adjacent IC chips or devices. For example, a low-power chip is any IC chip that generates on the order of about 1 W of heat, i.e., no more than about 5 W, during normal operation. Low-power chips may be passive devices located in the IC system 100, for example a memory device, such as RAM or flash memory, an I/O chip, or any other chip that does not generate over 5 W in normal operation.
In the embodiment shown in
The low-power chip 102 mounted on the second packaging substrate 140 may be encapsulated in a molding material 148 to protect the low-power chips 102. If desired, reliability of electrical connections 142 may be improved by protecting the electrical connections 142 with an encapsulant material. The molding or encapsulant material may be a resin, such as epoxy resin, acrylic resin, silicone resin, polyurethane resin, polyamide resin, polyimide resin, etc. Any other technically feasible packaging techniques may be used to protect the low-power chip 102 or electrical connections 142 of the low-power chip 102 to the first packaging substrate 110. While not shown, it is contemplated that the top side 150 of the molding material 148 facing away from the second packaging substrate 140 may be attached to a heat sink or other cooling mechanism to enhance the thermal transmittance of the IC system 100.
The low-power chip 102 is mounted opposite the high-power chip 101 in a stacked configuration, and is electrically connected to the high-power chip 101 and the PCB 190 via conductive traces 114 and conductive vias 123 formed in the first packaging substrate 110. The electrical connection between the high-power chip 101 and the first packaging substrate 110 may be made using any technically feasible approach known in the art. It is noted that conductive traces 114 and conductive vias 123, and configuration thereof, are exemplary approaches that can be used to electrically connect the high-power chip 101 to external components. Any known electrical connection with a different routing arrangement/configuration may be used in lieu of or in addition to the use of conductive traces 114 and conductive vias 123.
In the embodiment illustrated in
Shorter routing of interconnects between circuits results in faster signal propagation and reduction in noise, cross-talk, and other parasitics. In the field of IC packaging, parasitics are caused by the interconnection of a chip to external components, e.g., IC bond pads, bond wires, package leads, conductive traces, and the like. By stacking low-power chip 102 and high-power chip 101 in an overlapping configuration as illustrated in
The first packaging substrate 110 provides the IC system 100 with structural rigidity and an electrical interface for routing input and output signals as well as power between the high-power chip 101, the low-power chip 102, and the PCB 190. The first packaging substrate 110 may be a laminate substrate comprised of a stack of insulation layers 117 or laminates that are built up on the top surface 152 and bottom surface 154 of a core layer 119 in which the high-power chip 101 is embedded. The conductive traces 114 and the conductive vias 123 are formed between the insulation layers 117 to provide electrical communication between the high-power chip 101, the low-power chip 102, and the PCB 190. The high-power chip 101 can be embedded in the first packaging substrate 110 by forming a cavity or recessed opening in the core layer 119 using a wet or dry etching process. The cavity or recessed opening is sized for accommodation of the high-power chip 101. After the high-power chip 101 is formed in the core layer 119, the insulation layers 117 and electrical connections such as the conductive traces 114 and the conductive vias 123 are then formed around the high-power chip 101. While not discussed herein, it should be appreciated by a skilled artisan that the conductive traces 114 may be formed by any suitable process such as etching a copper foil bonded to one or more laminates of the first packaging substrate 110. The conductive vias 123 may be a copper-filled vias formed by electroplating process or any other suitable technique.
The high-power chip 101 may be located at a pre-determined depth in the first packaging substrate 110. It may be advantageous in some embodiments to place the high-power chip 101 at an elevation that is closer to the PCB 190 to promote heat dissipation into the PCB 190. It is also contemplated that the high-power chip 101 may not need to be fully embedded in the first packaging substrate 110. The top surface 152 of the high-power chip 101 may be flush with, slightly below or above the top surface 143 of the first packaging substrate 110. The elevation of the high-power chip 101 may vary depending upon the process scheme or application. In one embodiment, the high-power chip 101 may have a thickness “T1” of about 100 μm to about 200 μm, for example about 150 μm. The first packaging substrate 110 may have a thickness “T2” of about 300 μm to about 500 μm, such as about 400 μm. A thicker or thinner profile is contemplated depending upon application.
The heat distribution layer 202 is configured to conduct thermal energy generated by the high-power chip 101 away from the low-power chip 102, thereby reducing the risk of overheating the low-power chip 102 during operation of IC system. The heat distribution layer 102 distributes the heat into, and throughout the first packaging substrate 202 along the longitudinal direction of the first packaging substrate 110. The heat is then dissipated to the PCB 190 through the packaging leads 180. Due to the increased surface area of the heat distribution layer 202 within the first packaging substrate 110 for heat dissipation, thermal energy generated by the high-power chip 101 can be dissipated into the PCB 190 more efficiently.
The heat distribution layer 202 may be laterally extended in a plane parallel to the top surface 156 of the first packaging substrate 110. The heat distribution layer 202 may be formed using an electroplating process, a physical vapor deposition (PVD), or any other suitable deposition process during the fabrication of the first packaging substrate 110. The heat distribution layer 202 may have a length “L1” slightly shorter than the length of the first packaging substrate 110, but longer than the length of the high-power chip 101. In one example, the length “L1” of the heat distribution layer 202 is between about 20 μm and about 150 μm, for example, about 80 μm. While only one heat distribution layer 202 is shown, it is contemplated that two or more heat distribution layers may be used in the first packaging substrate 110 in any suitable arrangement to enhance heat removal from the high-power chip 101. For example, two or more heat distribution layers (not shown) may be attached to the bottom surface 158 of the high-power chip 101, with or without the heat distribution layer 202 attached to the top surface 156 of the high-power chip 101. Any additional heat distribution layer (if used) may extend laterally through the first packaging substrate 110 along a longitudinal direction of the first packaging substrate 110, or in any other arrangement depending upon the application. In some embodiments, the heat distribution layer 202 and/or any additional heat distribution layer (if used) may be formed from two or more layers of metallic foil, and the thickness of which can be readily determined by one of skill in the art given the footprint of the IC system 200 and the heat generation of the high-power chip 101 and the low-power chip 102. While not shown, it is contemplated that the heat distribution layer 202 may include through-holes to allow interconnects to run between the low-power chip 102 and the high-power chip 101 without contacting the heat distribution layer 202.
The high-power chip 101 is embedded within a first supporting substrate 310. The first supporting substrate 310 is comprised of the top insulation layer 302, the bottom insulation layer 304, and the molding material 305 sandwiched between the top insulation layer 302 and the bottom insulation layer 304. The molding material 305 encapsulates the high-power chip 101. Specifically, the molding material 305 substantially fills the spaces 306, 308 defined by the top insulation layer 302, the bottom insulation layer 304, and periphery 310 of the high-power chip 101, resulting in the high-power chip 101 surrounded by the molding material 305. While not shown, the top and bottom insulation layers 302, 304 may be a laminate structure comprised of a stack of insulation layers (such as the insulation layers 117 shown in
The bottom surface 354 of the molding material 305 may be substantially co-planar with the top surface of the bottom insulation layer 304, while the top surface 352 of the molding material 305 may be substantially co-planar with the bottom surface of the top insulation layer 302. In such a case, the high-power chip 101 may be separated from the top insulation layer 302 and/or the bottom insulation layer 304 by a desired distance. Alternatively, the top insulation layer 302 may be a continuous layer covering the top surface 352 of the molding material 305 and the top surface of the high-power chip 101 that is embedded within the molding material 305, while the bottom insulation layer 304 may be a continuous layer covering the bottom surface 354 of the molding material 305 and the bottom surface of the high-power chip 101 that is embedded within the molding material 305. In either case, the molding material 305 may include any suitable molding material known in the art that flows well and therefore minimizes the formation of any gaps. In one example, the molding material is a molding compound such as epoxy resin, acrylic resin, silicone resin, polyurethane resin, polyamide resin, polyimide resin, etc.
The top insulation layer 302 may include a top redistribution feature embedded therein to facilitate routing of electrical signals between the low-power chip 102, the high-power chip 101, and the PCB 190. In one embodiment, the top redistribution feature is an electrical conductive wire 312a laterally extended a desired length in a plane parallel to the top surface 352 of the molding material 305. In another embodiment, the top redistribution feature may include two or more electrical conductive wires (either coplanar or non coplanar wires) arranged in the top insulation layer 302 and electrically connected in a parallel relationship with each other by conductive vias 362. The use of the redistribution feature enables a reduction in the number of routing layers in the first supporting substrate 310 for the package system 300.
The electrical connections between the low-power chip 102, the high-power chip 101, and the PCB 190 can be made by any technically feasible chip package electrical connection known in the art. In one embodiment, the one or more top redistribution features 312a may connect respectively to solder bumps 342 and one or more bond pads 330 disposed on one side of the high-power chip 101 through conductive vias 344 and conductive vias 346, respectively. The one or more bond pads 330 are in electrical communication with one or more bond pads 368 disposed on the other side of the high-power chip 101 by means of through-silicon vias 344 formed through the high-power chip 101. Similarly, the one or more bond pads 368 are in electrical communication with the PCB 190 through conductive lines 350 and BGA 358. While not discussed herein, it is contemplated that the same electrical connections may be used to transmit power, ground and/or I/O signal between the low-power chip 102, the high-power chip 101, and the PCB 190.
Similarly, the bottom insulation layer 304 may include a bottom redistribution feature embedded therein to facilitate routing of electrical signals between the low-power chip 102, the high-power chip 101, and the PCB 190, thereby enabling a reduction in the number of routing layers in the first supporting substrate 310 for the package system 300. The bottom redistribution feature may be an electrical conductive wire 314a laterally extended a desired length in a plane parallel to the bottom surface 354 of the molding material 305. Alternatively, the bottom redistribution feature may include two or more electrical conductive wires (either coplanar or non coplanar wires) arranged in the bottom insulation layer 304 and electrically connected in a parallel relationship with each other by conductive vias 364, thereby enabling a reduction in the number of routing layers in the first supporting substrate 310 for the package system 300. The bottom redistribution feature may also serve to spread the heat generated by the high-power chip 101 into the bottom insulation layer 304. While not shown, it is contemplated that the top and bottom insulation layers 302, 304 may include one or more electrical traces, bond pad connectors, vias, wires, or any known structure, construction, arrangement in the art for physically transferring a signal or power from one point in a circuit to another. The top and bottom redistribution features may also be in any other arrangement/configuration that would increase thermal transmittance from the high-power chips 101 into the first supporting substrate 310.
With the top and bottom insulation layers 302, 304 and associated redistribution features embedded therein, the high-power chip 101 can be in electrical communication with the low-power chip 102 mounted on a second supporting substrate 340 (identical in structure and operation to the second packaging substrate 140 in
The set of heat distribution features may be thermal conductive vias formed by laser drilling or any other suitable technique. The thermal conductive vias is filled with a heat transmit media using any suitable technique such as an electroplating process. In one example, the thermal conductive vias is filled with a metal filler such as copper. However, any material with higher thermal conductivity than the first supporting substrate 310 may be used.
With the inventive configuration of the heat distribution features, the low-power chips 102 are not suffering the effects of overheating since the high-power chip 101 is embedded in the packaging substrate and the heat generated by the high-power chip 101 can be effectively dissipated into the PCB 190 through the heat distribution layer 202 as shown in
In sum, embodiments of the invention set forth an IC system in which one or more low-power chips can be positioned proximate high-power chips without suffering the effects of overheating. By having a heat distribution feature disposed adjacent to the one or more high-power chips embedded in a packaging substrate, the heat generated by the high-power chips can be effectively dissipated into the packaging substrate and then to a PCB, which serves as a heat sink for the IC system, thereby preventing heat transfer from the high-power chips to the low-power chips. As a result, the lifetime of the memory chip is extended.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
