Jean-Pierre Dolait

Person

Villeneuve-Loubet, FR

People

Patents Grantslast 30 patents

Information Patent Grant
SDRAM with command decoder coupled to address registers
- Patent number 6,910,096
- Issue date Jun 21, 2005
- Texas Instruments Incorporated
- Masashi Hashimoto
- G11 - INFORMATION STORAGE
Information Patent Grant
SDRAM with command decoder, address registers, multiplexer, and seq...
- Patent number 6,895,465
- Issue date May 17, 2005
- Texas Instruments Incorporated
- Masashi Hashimoto
- G11 - INFORMATION STORAGE
Information Patent Grant
Process of operating a DRAM system
- Patent number 6,748,483
- Issue date Jun 8, 2004
- Texas Instruments Incorporated
- Masashi Hashimoto
- G11 - INFORMATION STORAGE
Information Patent Grant
Synchronous DRAM with control data buffer
- Patent number 6,738,860
- Issue date May 18, 2004
- Texas Instruments Incorporated
- Masashi Hashimoto
- G11 - INFORMATION STORAGE
Information Patent Grant
Synchronous data system with control data buffer
- Patent number 6,735,667
- Issue date May 11, 2004
- Texas Instruments Incorporated
- Masashi Hashimoto
- G11 - INFORMATION STORAGE
Information Patent Grant
Process of using a DRAM with address control data
- Patent number 6,735,668
- Issue date May 11, 2004
- Texas Instruments Incorporated
- Masashi Hashimoto
- G11 - INFORMATION STORAGE
Information Patent Grant
Process for controlling reading data from a DRAM array
- Patent number 6,732,225
- Issue date May 4, 2004
- Texas Instruments Incorporated
- Masashi Hashimoto
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device for transferring streams of data
- Patent number 6,732,226
- Issue date May 4, 2004
- Texas Instruments Incorporated
- Masashi Hashimoto
- G11 - INFORMATION STORAGE
Information Patent Grant
System with control data buffer for transferring streams of data
- Patent number 6,732,224
- Issue date May 4, 2004
- Texas Instrument Incorporated
- Masashi Hashimoto
- G11 - INFORMATION STORAGE
Information Patent Grant
Synchronous data transfer system
- Patent number 6,728,828
- Issue date Apr 27, 2004
- Texas Instruments Incorporated
- Masashi Hashimoto
- G11 - INFORMATION STORAGE
Information Patent Grant
Synchronous DRAM system with control data
- Patent number 6,728,829
- Issue date Apr 27, 2004
- Texas Instruments Incorporated
- Masashi Hashimoto
- G11 - INFORMATION STORAGE
Information Patent Grant
Synchronous DRAM System with control data
- Patent number 6,662,291
- Issue date Dec 9, 2003
- Texas Instruments Incorporated
- Masashi Hashimoto
- G11 - INFORMATION STORAGE
Information Patent Grant
Synchronous DRAM device having a control data buffer
- Patent number 6,418,078
- Issue date Jul 9, 2002
- Texas Instruments Incorporated
- Masashi Hashimoto
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Process of synchronously writing data to a dynamic random access me...
- Patent number 6,188,635
- Issue date Feb 13, 2001
- Texas Instruments Incorporated
- Masashi Hashimoto
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Memory circuit accommodating both serial and random access, having...
- Patent number 5,805,518
- Issue date Sep 8, 1998
- Texas Instruments Incorporated
- Masashi Hashimoto
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Process of transfering streams of data to and from a random access...
- Patent number 5,768,205
- Issue date Jun 16, 1998
- Texas Instruments Incorporated
- Masashi Hashimoto
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Synchronous data transfer system
- Patent number 5,684,753
- Issue date Nov 4, 1997
- Texas Instruments Incorporated
- Masashi Hashimoto
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
System transferring streams of data
- Patent number 5,680,358
- Issue date Oct 21, 1997
- Texas Instruments Incorporated
- Masashi Hashimoto
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Synchronous dynamic random access memory device
- Patent number 5,680,369
- Issue date Oct 21, 1997
- Texas Instruments Incorporated
- Masashi Hashimoto
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Dram system with control data
- Patent number 5,680,368
- Issue date Oct 21, 1997
- Texas Instruments Incorporated
- Masashi Hashimoto
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Synchronous DRAM device having a control data buffer
- Patent number 5,680,370
- Issue date Oct 21, 1997
- Texas Instruments Incorporated
- Masashi Hashimoto
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Process for controlling writing data to a DRAM array
- Patent number 5,680,367
- Issue date Oct 21, 1997
- Texas Instruments Incorporated
- Masashi Hashimoto
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Synchronous DRAM responsive to first and second clock signals
- Patent number 5,636,176
- Issue date Jun 3, 1997
- Texas Instruments Incorporated
- Masashi Hashimoto
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Memory circuit accommodating both serial and random access includin...
- Patent number 5,587,962
- Issue date Dec 24, 1996
- Texas Instruments Incorporated
- Masashi Hashimoto
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Semiconductor memory chip
- Patent number 5,400,288
- Issue date Mar 21, 1995
- Texas Instruments Incorporated
- Masashi Hashimoto
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Video frame storage system
- Patent number 5,093,807
- Issue date Mar 3, 1992
- Texas Instruments Incorporated
- Masashi Hashimoto
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS

Patents Applicationslast 30 patents

Information Patent Application
Synchronous dram system with control data
- Publication number 20050182914
- Publication date Aug 18, 2005
- Masashi Hashimoto
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Synchronous DRAM system with control data
- Publication number 20040186950
- Publication date Sep 23, 2004
- Masashi Hashimoto
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
System with control data buffer for transferring streams of data
- Publication number 20030208669
- Publication date Nov 6, 2003
- Masashi Hashimoto
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Synchronous DRAM with control data buffer
- Publication number 20030200381
- Publication date Oct 23, 2003
- Masashi Hashimoto
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Synchronous dram system with control data
- Publication number 20030200416
- Publication date Oct 23, 2003
- Masashi Hashimoto
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Synchronous data transfer system
- Publication number 20030200415
- Publication date Oct 23, 2003
- Masashi Hashimoto
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Process for controlling reading data from a DRAM array
- Publication number 20030200417
- Publication date Oct 23, 2003
- Masashi Hashimoto
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
RAM with fewer address terminals than data terminals
- Publication number 20030196067
- Publication date Oct 16, 2003
- Masashi Hashimoto
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Memory device for transferring streams of data
- Publication number 20030196068
- Publication date Oct 16, 2003
- Masashi Hashimoto
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Synchronous data system with control data buffer
- Publication number 20030196034
- Publication date Oct 16, 2003
- Masashi Hashimoto
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Process of using a dram with address control data
- Publication number 20030196069
- Publication date Oct 16, 2003
- Masashi Hashimoto
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Frame memory circuit
- Publication number 20030037219
- Publication date Feb 20, 2003
- Masashi Hashimoto
- G11 - INFORMATION STORAGE
Information Patent Application
Frame memory circuit
- Publication number 20010000817
- Publication date May 3, 2001
- Masashi Hashimoto
- G11 - INFORMATION STORAGE

Jean-Pierre Dolait

Person

Patents Grantslast 30 patents

SDRAM with command decoder coupled to address registers

SDRAM with command decoder, address registers, multiplexer, and seq...

Process of operating a DRAM system

Synchronous DRAM with control data buffer

Synchronous data system with control data buffer

Process of using a DRAM with address control data

Process for controlling reading data from a DRAM array

Memory device for transferring streams of data

System with control data buffer for transferring streams of data

Synchronous data transfer system

Synchronous DRAM system with control data

Synchronous DRAM System with control data

Synchronous DRAM device having a control data buffer

Process of synchronously writing data to a dynamic random access me...

Memory circuit accommodating both serial and random access, having...

Process of transfering streams of data to and from a random access...

Synchronous data transfer system

System transferring streams of data

Synchronous dynamic random access memory device

Dram system with control data

Synchronous DRAM device having a control data buffer

Process for controlling writing data to a DRAM array

Synchronous DRAM responsive to first and second clock signals

Memory circuit accommodating both serial and random access includin...

Semiconductor memory chip

Video frame storage system

Patents Applicationslast 30 patents

Synchronous dram system with control data

Synchronous DRAM system with control data

System with control data buffer for transferring streams of data

Synchronous DRAM with control data buffer

Synchronous dram system with control data

Synchronous data transfer system

Process for controlling reading data from a DRAM array

RAM with fewer address terminals than data terminals

Memory device for transferring streams of data

Synchronous data system with control data buffer

Process of using a dram with address control data

Frame memory circuit

Frame memory circuit