Jeff Rooney

Person

Blaine, MN, US

People

Patents Grantslast 30 patents

Information Patent Grant
Programmable on-chip logic analyzer apparatus, systems, and methods
- Patent number 8,575,958
- Issue date Nov 5, 2013
- Micron Technology, Inc.
- Kirsten S. Lunzer
- G01 - MEASURING TESTING
Information Patent Grant
Programmable on-chip logic analyzer apparatus, systems, and methods
- Patent number 7,944,234
- Issue date May 17, 2011
- Micron Technology, Inc.
- Kirsten S. Lunzer
- G01 - MEASURING TESTING
Information Patent Grant
Integrated testing apparatus, systems, and methods
- Patent number 7,707,473
- Issue date Apr 27, 2010
- Micron Technology, Inc.
- Paul A. LaBerge
- G11 - INFORMATION STORAGE
Information Patent Grant
Providing memory test patterns for DLL calibration
- Patent number 7,694,202
- Issue date Apr 6, 2010
- Micron Technology, Inc.
- Travis E. Swanson
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for dynamic buffer allocation
- Patent number 7,590,764
- Issue date Sep 15, 2009
- Micron Technology, Inc.
- Jeffrey Jay Rooney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic buffer allocation for a computer system
- Patent number 6,601,118
- Issue date Jul 29, 2003
- Micron Technology, Inc.
- Jeffrey Jay Rooney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for flexibly allocating request/grant pins between multip...
- Patent number 6,389,492
- Issue date May 14, 2002
- Micron Technology, Inc.
- Douglas A. Larson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for flexibly allocating request/grant pins between multiple...
- Patent number 6,385,680
- Issue date May 7, 2002
- Micron Technology, Inc.
- Douglas A. Larson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic buffer allocation for a computer system
- Patent number 6,243,769
- Issue date Jun 5, 2001
- Micron Technology, Inc.
- Jeffrey Jay Rooney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for dynamic buffer allocation comprising control logic for c...
- Patent number 6,073,190
- Issue date Jun 6, 2000
- Micron Electronics, Inc.
- Jeffrey Jay Rooney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for aligning a control signal and a clock signal
- Patent number 5,857,095
- Issue date Jan 5, 1999
- Micron Electronics, Inc.
- Joseph M. Jeddeloh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller with low skew control signal
- Patent number 5,819,076
- Issue date Oct 6, 1998
- Micron Electronics, Inc.
- Joseph M. Jeddeloh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller with low skew control signal
- Patent number 5,692,165
- Issue date Nov 25, 1997
- Micron Electronics Inc.
- Joseph M. Jeddeloh
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PROGRAMMABLE ON-CHIP LOGIC ANALYZER APPARATUS, SYSTEMS, AND METHODS
- Publication number 20110215833
- Publication date Sep 8, 2011
- Kirsten S. Lunzer
- G01 - MEASURING TESTING
Information Patent Application
PROGRAMMABLE ON-CHIP LOGIC ANALYZER APPARATUS, SYSTEMS, AND METHODS
- Publication number 20090237110
- Publication date Sep 24, 2009
- Micron Technology, Inc.
- Kirsten S. Lunzer
- G01 - MEASURING TESTING
Information Patent Application
Integrated testing apparatus, systems, and methods
- Publication number 20080052585
- Publication date Feb 28, 2008
- Micron Technology, Inc.
- Paul A. LaBerge
- G01 - MEASURING TESTING
Information Patent Application
Providing memory test patterns for DLL calibration
- Publication number 20050162948
- Publication date Jul 28, 2005
- Travis Swanson
- G11 - INFORMATION STORAGE
Information Patent Application
Dynamic buffer allocation for a computer system
- Publication number 20040054823
- Publication date Mar 18, 2004
- Jeffrey Jay Rooney
- G06 - COMPUTING CALCULATING COUNTING

Jeff Rooney

Person

Patents Grantslast 30 patents

Programmable on-chip logic analyzer apparatus, systems, and methods

Programmable on-chip logic analyzer apparatus, systems, and methods

Integrated testing apparatus, systems, and methods

Providing memory test patterns for DLL calibration

System and method for dynamic buffer allocation

Dynamic buffer allocation for a computer system

Apparatus for flexibly allocating request/grant pins between multip...

Method for flexibly allocating request/grant pins between multiple...

Dynamic buffer allocation for a computer system

System for dynamic buffer allocation comprising control logic for c...

Method for aligning a control signal and a clock signal

Memory controller with low skew control signal

Memory controller with low skew control signal

Patents Applicationslast 30 patents

PROGRAMMABLE ON-CHIP LOGIC ANALYZER APPARATUS, SYSTEMS, AND METHODS

PROGRAMMABLE ON-CHIP LOGIC ANALYZER APPARATUS, SYSTEMS, AND METHODS

Integrated testing apparatus, systems, and methods

Providing memory test patterns for DLL calibration

Dynamic buffer allocation for a computer system