Jeffrey D. Chamberlain

Person

Tracy, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Cache line demote infrastructure for multi-processor pipelines
- Patent number 12,066,939
- Issue date Aug 20, 2024
- Intel Corporation
- Rahul R. Shah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Link affinitization to reduce transfer latency
- Patent number 11,966,330
- Issue date Apr 23, 2024
- Intel Corporation
- Vinit Mathew Abraham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Function as a service (FaaS) system enhancements
- Patent number 11,922,220
- Issue date Mar 5, 2024
- Intel Corporation
- Mohammad R. Haghighat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple dies hardware processors and methods
- Patent number 11,899,615
- Issue date Feb 13, 2024
- Intel Corporation
- Nevine Nassif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple dies hardware processors and methods
- Patent number 11,586,579
- Issue date Feb 21, 2023
- Intel Corporation
- Nevine Nassif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple dies hardware processors and methods
- Patent number 11,294,852
- Issue date Apr 5, 2022
- Intel Corporation
- Nevine Nassif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, apparatus and method for adaptive interconnect routing
- Patent number 11,256,657
- Issue date Feb 22, 2022
- Intel Corporation
- Tejpal Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for per-agent control and quality of service of s...
- Patent number 10,936,490
- Issue date Mar 2, 2021
- Intel Corporation
- Andrew J. Herdrich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple dies hardware processors and methods
- Patent number 10,795,853
- Issue date Oct 6, 2020
- Intel Corporation
- Nevine Nassif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalably mechanism to implement an instruction that monitors for wr...
- Patent number 10,705,961
- Issue date Jul 7, 2020
- Intel Corporation
- Yen-Cheng Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimized caching agent with integrated directory cache
- Patent number 10,339,060
- Issue date Jul 2, 2019
- Intel Corporation
- Bahaa Fahim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtual retry queue
- Patent number 10,338,974
- Issue date Jul 2, 2019
- Intel Corporation
- Bahaa Fahim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Value of forward state by increasing local caching agent forwarding
- Patent number 10,204,049
- Issue date Feb 12, 2019
- Intel Corporation
- Vedaraman Geetha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two level memory full line writes
- Patent number 10,140,213
- Issue date Nov 27, 2018
- Intel Corporation
- Robert G. Blankenship
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache allocation with code and data prioritization
- Patent number 10,089,229
- Issue date Oct 2, 2018
- Intel Corporation
- Andrew J. Herdrich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, apparatus and system for modular on-die coherent interconne...
- Patent number 9,921,989
- Issue date Mar 20, 2018
- Intel Corporation
- Krishnakumar Ganapathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two level memory full line writes
- Patent number 9,619,396
- Issue date Apr 11, 2017
- Intel Corporation
- Robert G. Blankenship
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, apparatus and system for optimizing cache memory transactio...
- Patent number 9,606,925
- Issue date Mar 28, 2017
- Intel Corporation
- Bahaa Fahim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache allocation with code and data prioritization
- Patent number 9,563,564
- Issue date Feb 7, 2017
- Intel Corporation
- Andrew J. Herdrich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache coherency apparatus and method minimizing memory writeback op...
- Patent number 9,436,605
- Issue date Sep 6, 2016
- Intel Corporation
- Jeffrey D. Chamberlain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inclusive and non-inclusive tracking of local cache lines to avoid...
- Patent number 9,418,009
- Issue date Aug 16, 2016
- Intel Corporation
- Adrian C. Moga
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple-queue multiple-resource entry sleep and wakeup for power s...
- Patent number 9,207,753
- Issue date Dec 8, 2015
- Intel Corporation
- James R. Vash
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Caching agent for deadlock prevention in a processor by allowing re...
- Patent number 9,189,296
- Issue date Nov 17, 2015
- Intel Corporation
- Bahaa Fahim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple-queue multiple-resource entry sleep and wakeup for power s...
- Patent number 8,868,951
- Issue date Oct 21, 2014
- Intel Corporation
- James R. Vash
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for processing a predicated instruction using...
- Patent number 6,883,089
- Issue date Apr 19, 2005
- Intel Corporation
- Ralph Kling
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MULTIPLE DIES HARDWARE PROCESSORS AND METHODS
- Publication number 20230169032
- Publication date Jun 1, 2023
- Intel Corporation
- NEVINE NASSIF
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE DIES HARDWARE PROCESSORS AND METHODS
- Publication number 20220050805
- Publication date Feb 17, 2022
- Intel Corporation
- NEVINE NASSIF
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems, Apparatuses, and Methods for Resource Bandwidth Enforcement
- Publication number 20210374848
- Publication date Dec 2, 2021
- Intel Corporation
- Andrew HERDRICH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FUNCTION AS A SERVICE (FAAS) SYSTEM ENHANCEMENTS
- Publication number 20210263779
- Publication date Aug 26, 2021
- Intel Corporation
- Mohammad R. Haghighat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE LINE DEMOTE INFRASTRUCTURE FOR MULTI-PROCESSOR PIPELINES
- Publication number 20210073129
- Publication date Mar 11, 2021
- Intel Corporation
- Rahul R. SHAH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE DIES HARDWARE PROCESSORS AND METHODS
- Publication number 20200334196
- Publication date Oct 22, 2020
- Intel Corporation
- NEVINE NASSIF
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System, Apparatus And Method For Adaptive Interconnect Routing
- Publication number 20200311018
- Publication date Oct 1, 2020
- Tejpal Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LINK AFFINITIZATION TO REDUCE TRANSFER LATENCY
- Publication number 20200301830
- Publication date Sep 24, 2020
- Intel Corporation
- Vinit MATHEW ABRAHAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUFFERED INTERCONNECT FOR HIGHLY SCALABLE ON-DIE FABRIC
- Publication number 20190236038
- Publication date Aug 1, 2019
- Swadesh Choudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR PER-AGENT CONTROL AND QUALITY OF SERVICE OF S...
- Publication number 20180373633
- Publication date Dec 27, 2018
- Intel Corporation
- Andrew J. Herdrich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZED CACHING AGENT WITH INTEGRATED DIRECTORY CACHE
- Publication number 20180189180
- Publication date Jul 5, 2018
- Intel Corporation
- Bahaa Fahim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE DIES HARDWARE PROCESSORS AND METHODS
- Publication number 20180101502
- Publication date Apr 12, 2018
- NEVINE NASSIF
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VALUE OF FORWARD STATE BY INCREASING LOCAL CACHING AGENT FORWARDING
- Publication number 20180081808
- Publication date Mar 22, 2018
- Intel Corporation
- Vedaraman GEETHA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO LEVEL MEMORY FULL LINE WRITES
- Publication number 20170337134
- Publication date Nov 23, 2017
- Intel Corporation
- Robert G. Blankenship
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE ALLOCATION WITH CODE AND DATA PRIORITIZATION
- Publication number 20170192887
- Publication date Jul 6, 2017
- Intel Corporation
- ANDREW J. HERDRICH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE ALLOCATION WITH CODE AND DATA PRIORITIZATION
- Publication number 20160299849
- Publication date Oct 13, 2016
- Intel Corporation
- ANDREW J. HERDRICH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS AND SYSTEM FOR OPTIMIZING CACHE MEMORY TRANSACTI...
- Publication number 20160283382
- Publication date Sep 29, 2016
- Bahaa Fahim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO LEVEL MEMORY FULL LINE WRITES
- Publication number 20160283388
- Publication date Sep 29, 2016
- Intel Corporation
- Robert G. Blankenship
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems, Apparatuses, and Methods for Resource Bandwidth Enforcement
- Publication number 20160284021
- Publication date Sep 29, 2016
- Andrew HERDRICH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS AND SYSTEM FOR MODULAR ON-DIE COHERENT INTERCONNECT
- Publication number 20160012010
- Publication date Jan 14, 2016
- Krishnakumar GANAPATHY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Inclusive/Non Inclusive Tracking of Local Cache Lines To Avoid Near...
- Publication number 20150186275
- Publication date Jul 2, 2015
- Adrian C. Moga
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEADLOCK PREVENTION IN A PROCESSOR
- Publication number 20150186191
- Publication date Jul 2, 2015
- Intel Corporation
- Bahaa Fahim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE COHERENCY APPARATUS AND METHOD MINIMIZING MEMORY WRITEBACK OP...
- Publication number 20150178206
- Publication date Jun 25, 2015
- Jeffrey D. Chamberlain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE-QUEUE MULTIPLE-RESOURCE ENTRY SLEEP AND WAKEUP FOR POWER S...
- Publication number 20150160720
- Publication date Jun 11, 2015
- James R. Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VIRTUAL RETRY QUEUE
- Publication number 20150128142
- Publication date May 7, 2015
- Bahaa Fahim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLY MECHANISM TO IMPLEMENT AN INSTRUCTION THAT MONITORS FOR WR...
- Publication number 20150095580
- Publication date Apr 2, 2015
- Intel Corporation
- Yen-Cheng Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISM TO IMPROVE INPUT/OUTPUT WRITE BANDWIDTH IN SCALABLE SYSTE...
- Publication number 20140281270
- Publication date Sep 18, 2014
- Henk G. Neefs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE-QUEUE MULTIPLE-RESOURCE ENTRY SLEEP AND WAKEUP FOR POWER S...
- Publication number 20110161705
- Publication date Jun 30, 2011
- James R. Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for processing a predicated instruction using...
- Publication number 20020087847
- Publication date Jul 4, 2002
- Ralph Kling
- G06 - COMPUTING CALCULATING COUNTING

Jeffrey D. Chamberlain

Person

Patents Grantslast 30 patents

Cache line demote infrastructure for multi-processor pipelines

Link affinitization to reduce transfer latency

Function as a service (FaaS) system enhancements

Multiple dies hardware processors and methods

Multiple dies hardware processors and methods

Multiple dies hardware processors and methods

System, apparatus and method for adaptive interconnect routing

System and method for per-agent control and quality of service of s...

Multiple dies hardware processors and methods

Scalably mechanism to implement an instruction that monitors for wr...

Optimized caching agent with integrated directory cache

Virtual retry queue

Value of forward state by increasing local caching agent forwarding

Two level memory full line writes

Cache allocation with code and data prioritization

Method, apparatus and system for modular on-die coherent interconne...

Two level memory full line writes

Method, apparatus and system for optimizing cache memory transactio...

Cache allocation with code and data prioritization

Cache coherency apparatus and method minimizing memory writeback op...

Inclusive and non-inclusive tracking of local cache lines to avoid...

Multiple-queue multiple-resource entry sleep and wakeup for power s...

Caching agent for deadlock prevention in a processor by allowing re...

Multiple-queue multiple-resource entry sleep and wakeup for power s...

Method and apparatus for processing a predicated instruction using...

Patents Applicationslast 30 patents

MULTIPLE DIES HARDWARE PROCESSORS AND METHODS

MULTIPLE DIES HARDWARE PROCESSORS AND METHODS

Systems, Apparatuses, and Methods for Resource Bandwidth Enforcement

FUNCTION AS A SERVICE (FAAS) SYSTEM ENHANCEMENTS

CACHE LINE DEMOTE INFRASTRUCTURE FOR MULTI-PROCESSOR PIPELINES

MULTIPLE DIES HARDWARE PROCESSORS AND METHODS

System, Apparatus And Method For Adaptive Interconnect Routing

LINK AFFINITIZATION TO REDUCE TRANSFER LATENCY

BUFFERED INTERCONNECT FOR HIGHLY SCALABLE ON-DIE FABRIC

SYSTEM AND METHOD FOR PER-AGENT CONTROL AND QUALITY OF SERVICE OF S...

OPTIMIZED CACHING AGENT WITH INTEGRATED DIRECTORY CACHE

MULTIPLE DIES HARDWARE PROCESSORS AND METHODS

VALUE OF FORWARD STATE BY INCREASING LOCAL CACHING AGENT FORWARDING

TWO LEVEL MEMORY FULL LINE WRITES

CACHE ALLOCATION WITH CODE AND DATA PRIORITIZATION

CACHE ALLOCATION WITH CODE AND DATA PRIORITIZATION

METHOD, APPARATUS AND SYSTEM FOR OPTIMIZING CACHE MEMORY TRANSACTI...

TWO LEVEL MEMORY FULL LINE WRITES

Systems, Apparatuses, and Methods for Resource Bandwidth Enforcement

METHOD, APPARATUS AND SYSTEM FOR MODULAR ON-DIE COHERENT INTERCONNECT

Inclusive/Non Inclusive Tracking of Local Cache Lines To Avoid Near...

DEADLOCK PREVENTION IN A PROCESSOR

CACHE COHERENCY APPARATUS AND METHOD MINIMIZING MEMORY WRITEBACK OP...

MULTIPLE-QUEUE MULTIPLE-RESOURCE ENTRY SLEEP AND WAKEUP FOR POWER S...

VIRTUAL RETRY QUEUE

SCALABLY MECHANISM TO IMPLEMENT AN INSTRUCTION THAT MONITORS FOR WR...

MECHANISM TO IMPROVE INPUT/OUTPUT WRITE BANDWIDTH IN SCALABLE SYSTE...

MULTIPLE-QUEUE MULTIPLE-RESOURCE ENTRY SLEEP AND WAKEUP FOR POWER S...

Method and apparatus for processing a predicated instruction using...