Jeffrey E. Brighton

Person

Katy, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
MOSFET with source side only stress
- Patent number 9,412,869
- Issue date Aug 9, 2016
- Texas Instruments Incorporated
- Samuel Zafar Nawaz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
MOSFET with source side only stress
- Patent number 8,928,047
- Issue date Jan 6, 2015
- Texas Instruments Incorporated
- Samuel Zafar Nawaz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Warpage control features on the bottomside of TSV die lateral to pr...
- Patent number 8,344,493
- Issue date Jan 1, 2013
- Texas Instruments Incorporated
- Jeffrey Alan West
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing a bipolar junction transistor including und...
- Patent number 6,713,361
- Issue date Mar 30, 2004
- Texas Instruments Incorporated
- Samuel Z. Nawaz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pillar alignment and formation process
- Patent number 5,436,199
- Issue date Jul 25, 1995
- Texas Instruments Incorporated
- Jeffrey E. Brighton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned tungsten-filled via
- Patent number 5,212,352
- Issue date May 18, 1993
- Texas Instruments Incorporated
- Jeffrey E. Brighton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for and products having self-aligned conductive pillars on...
- Patent number 5,132,775
- Issue date Jul 21, 1992
- Texas Instruments Incorporated
- Jeffrey E. Brighton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Polysilicon self-aligned bipolar device including trench isolation...
- Patent number 5,104,816
- Issue date Apr 14, 1992
- Texas Instruments Incorporated
- Douglas P. Verret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Product of pillar alignment and formation process
- Patent number 5,025,303
- Issue date Jun 18, 1991
- Texas Instruments Incorporated
- Jeffrey E. Brighton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned tungsten-filled via process and via formed thereby
- Patent number 4,996,133
- Issue date Feb 26, 1991
- Texas Instruments Incorporated
- Jeffrey E. Brighton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
VLSI self-aligned bipolar transistor
- Patent number 4,979,010
- Issue date Dec 18, 1990
- Texas Instruments Incorporated
- Jeffrey E. Brighton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for planarization of a semiconductor device prior to metalli...
- Patent number 4,966,865
- Issue date Oct 30, 1990
- Texas Instruments Incorporated
- Michael T. Welch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned nonnested sloped via
- Patent number 4,931,144
- Issue date Jun 5, 1990
- Texas Instruments Incorporated
- Jeffrey E. Brighton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for forming self-aligned conductive pillars on interconnects
- Patent number 4,866,008
- Issue date Sep 12, 1989
- Texas Instruments Incorporated
- Jeffrey E. Brighton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned nonnested sloped via
- Patent number 4,842,991
- Issue date Jun 27, 1989
- Texas Instruments Incorporated
- Jeffrey E. Brighton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making single polysilicon self-aligned transistor
- Patent number 4,839,305
- Issue date Jun 13, 1989
- Texas Instruments Incorporated
- Jeffrey E. Brighton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bipolar transistor in isolation well with angled corners
- Patent number 4,799,099
- Issue date Jan 17, 1989
- Texas Instruments Incorporated
- Douglas P. Verret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for planarization of a semiconductor device prior to metalli...
- Patent number 4,795,722
- Issue date Jan 3, 1989
- Texas Instruments Incorporated
- Michael T. Welch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned silicide in a polysilicon self-aligned bipolar transistor
- Patent number 4,789,885
- Issue date Dec 6, 1988
- Texas Instruments Incorporated
- Jeffrey E. Brighton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for etching contact vias in a semiconductor device
- Patent number 4,753,709
- Issue date Jun 28, 1988
- Texas Instuments Incorporated
- Michael T. Welch
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
MOSFET WITH SOURCE SIDE ONLY STRESS
- Publication number 20150087127
- Publication date Mar 26, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Samuel Zafar Nawaz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Post-Polymer Revealing of Through-Substrate Via Tips
- Publication number 20140154880
- Publication date Jun 5, 2014
- TEXAS INSTRUMENTS INCORPORATED
- JEFFREY E. BRIGHTON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POST-POLYMER REVEALING OF THROUGH-SUBSTRATE VIA TIPS
- Publication number 20130062736
- Publication date Mar 14, 2013
- TEXAS INSTRUMENTS INCORPORATED
- JEFFREY E. BRIGHTON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WARPAGE CONTROL FEATURES ON THE BOTTOMSIDE OF TSV DIE LATERAL TO PR...
- Publication number 20120175774
- Publication date Jul 12, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Jeffrey Alan West
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MOSFET WITH SOURCE SIDE ONLY STRESS
- Publication number 20120146054
- Publication date Jun 14, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Samuel Zafar Nawaz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for manufacturing a bipolar junction transistor
- Publication number 20020039815
- Publication date Apr 4, 2002
- Samuel Z. Nawaz
- H01 - BASIC ELECTRIC ELEMENTS

Jeffrey E. Brighton

Person

Patents Grantslast 30 patents

MOSFET with source side only stress

MOSFET with source side only stress

Warpage control features on the bottomside of TSV die lateral to pr...

Method of manufacturing a bipolar junction transistor including und...

Pillar alignment and formation process

Self-aligned tungsten-filled via

Methods for and products having self-aligned conductive pillars on...

Polysilicon self-aligned bipolar device including trench isolation...

Product of pillar alignment and formation process

Self-aligned tungsten-filled via process and via formed thereby

VLSI self-aligned bipolar transistor

Method for planarization of a semiconductor device prior to metalli...

Self-aligned nonnested sloped via

Methods for forming self-aligned conductive pillars on interconnects

Self-aligned nonnested sloped via

Method of making single polysilicon self-aligned transistor

Bipolar transistor in isolation well with angled corners

Method for planarization of a semiconductor device prior to metalli...

Self-aligned silicide in a polysilicon self-aligned bipolar transistor

Method for etching contact vias in a semiconductor device

Patents Applicationslast 30 patents

MOSFET WITH SOURCE SIDE ONLY STRESS

Post-Polymer Revealing of Through-Substrate Via Tips

POST-POLYMER REVEALING OF THROUGH-SUBSTRATE VIA TIPS

WARPAGE CONTROL FEATURES ON THE BOTTOMSIDE OF TSV DIE LATERAL TO PR...

MOSFET WITH SOURCE SIDE ONLY STRESS

Method for manufacturing a bipolar junction transistor