Jeffrey H. Seltzer

Person

Los Gatos, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Automated pipeline insertion on a bus
- Patent number 10,970,446
- Issue date Apr 6, 2021
- XLNX, INC.
- Jeffrey H. Seltzer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface firewall for an integrated circuit of an expansion card
- Patent number 10,819,680
- Issue date Oct 27, 2020
- Xilinx, Inc.
- Sonal Santan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System level circuit design
- Patent number 8,769,449
- Issue date Jul 1, 2014
- Xilinx, Inc.
- Adam P. Donlin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Deadlock-resistant bus bridge with pipeline-restricted address ranges
- Patent number 7,970,977
- Issue date Jun 28, 2011
- Xilinx, Inc.
- Kam-Wing Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Embedded function units with decoding
- Patent number 6,980,030
- Issue date Dec 27, 2005
- Xilinx, Inc.
- Frank C. Wirtz, II
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock enable control circuit for flip flops
- Patent number 6,466,049
- Issue date Oct 15, 2002
- Xilinx, Inc.
- Sholeh Diba
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method of minimizing power use in programmable logic devices
- Patent number 6,172,518
- Issue date Jan 9, 2001
- Xilinx, Inc.
- Jesse H. Jenkins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and system for HDL global signal simulation and verification
- Patent number 5,991,523
- Issue date Nov 23, 1999
- Xilinx, Inc.
- Anthony D. Williams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Product term exporting mechanism and method improvement in an EPLD...
- Patent number 5,969,539
- Issue date Oct 19, 1999
- Xilinx, Inc.
- Isaak Veytsman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Structure and method for arithmetic function implementation in an E...
- Patent number 5,821,774
- Issue date Oct 13, 1998
- Xilinx, Inc.
- Isaak Veytsman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit for partially reprogramming an operational programmable log...
- Patent number 5,764,076
- Issue date Jun 9, 1998
- Xilinx, Inc.
- Napoleon W. Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Macrocell with product-term cascade and improved flip flop utilization
- Patent number 5,565,792
- Issue date Oct 15, 1996
- Xilinx, Inc.
- David Chiang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High speed product term allocation structure supporting logic itera...
- Patent number 5,563,529
- Issue date Oct 8, 1996
- Xilinx, Inc.
- Jeffrey H. Seltzer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Macrocell with product-term cascade and improved flip flop utilization
- Patent number 5,357,153
- Issue date Oct 18, 1994
- Xilinx, Inc.
- David Chiang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Input circuit block and method for PLDs with register clock enable...
- Patent number 5,302,866
- Issue date Apr 12, 1994
- Xilinx, Inc.
- David Chiang
- H03 - BASIC ELECTRONIC CIRCUITRY

Jeffrey H. Seltzer

Person

Patents Grantslast 30 patents

Automated pipeline insertion on a bus

Interface firewall for an integrated circuit of an expansion card

System level circuit design

Deadlock-resistant bus bridge with pipeline-restricted address ranges

Embedded function units with decoding

Clock enable control circuit for flip flops

Method of minimizing power use in programmable logic devices

Method and system for HDL global signal simulation and verification

Product term exporting mechanism and method improvement in an EPLD...

Structure and method for arithmetic function implementation in an E...

Circuit for partially reprogramming an operational programmable log...

Macrocell with product-term cascade and improved flip flop utilization

High speed product term allocation structure supporting logic itera...

Macrocell with product-term cascade and improved flip flop utilization

Input circuit block and method for PLDs with register clock enable...