Jen-Tzu YANG

Person

Hemei Township, TW

People

Patents Grantslast 30 patents

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- Patent number 12,063,039
- Issue date Aug 13, 2024
- Mediatek Inc.
- Wei-Min Hsu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Interconnect landing method for RRAM technology
- Patent number 11,889,705
- Issue date Jan 30, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hsia-Wei Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flat bottom electrode via (BEVA) top surface for memory
- Patent number 11,844,286
- Issue date Dec 12, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hsia-Wei Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ultra-reliable and low latency communications local breakout method...
- Patent number 11,784,873
- Issue date Oct 10, 2023
- Wistron NeWeb Corporation
- Jen-Shun Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Flat bottom electrode via (BEVA) top surface for memory
- Patent number 11,751,485
- Issue date Sep 5, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hsia-Wei Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Step height mitigation in resistive random access memory structures
- Patent number 11,678,592
- Issue date Jun 13, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd
- Wei-Ming Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Resource management system and resource management method
- Patent number 11,632,329
- Issue date Apr 18, 2023
- Wistron NeWeb Corporation
- Jen-Shun Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Level converting enable latch
- Patent number 11,606,093
- Issue date Mar 14, 2023
- Mediatek Inc.
- Wei-Min Hsu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Processing circuit using delay element coupled between control term...
- Patent number 11,264,974
- Issue date Mar 1, 2022
- Mediatek Inc.
- Jen-Hang Yang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for forming a flat bottom electrode via (BEVA) top surface f...
- Patent number 11,201,281
- Issue date Dec 14, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hsia-Wei Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect landing method for RRAM technology
- Patent number 11,094,744
- Issue date Aug 17, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hsia-Wei Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned insulated film for high-K metal gate device
- Patent number 11,094,545
- Issue date Aug 17, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd
- Jin-Aun Ng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Step height mitigation in resistive random access memory structures
- Patent number 11,038,108
- Issue date Jun 15, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd
- Wei-Ming Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and manufacturing method thereof
- Patent number 11,004,975
- Issue date May 11, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd
- Kuo-Chi Tu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect landing method for RRAM technology
- Patent number 10,903,274
- Issue date Jan 26, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd
- Hsia-Wei Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for reading RRAM cell
- Patent number 10,796,759
- Issue date Oct 6, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chin-Chieh Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for forming a flat bottom electrode via (BEVA) top surface f...
- Patent number 10,763,426
- Issue date Sep 1, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hsia-Wei Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and manufacturing method thereof
- Patent number 10,727,337
- Issue date Jul 28, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd
- Kuo-Chi Tu
- G11 - INFORMATION STORAGE
Information Patent Grant
Full adder circuits with reduced delay
- Patent number 10,620,915
- Issue date Apr 14, 2020
- Mediatek Inc.
- Ying-Chun Wei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for forming a flat bottom electrode via (BEVA) top surface f...
- Patent number 10,566,519
- Issue date Feb 18, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hsia-Wei Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect landing method for RRAM technology
- Patent number 10,566,387
- Issue date Feb 18, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hsia-Wei Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Cell layout utilizing boundary cell with mixed poly pitch within in...
- Patent number 10,445,453
- Issue date Oct 15, 2019
- Mediatek Inc.
- Jen-Hang Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system of device-to-device tunnel establishment between...
- Patent number 10,425,251
- Issue date Sep 24, 2019
- Wistron NeWeb Corporation
- Chui-Chu Cheng
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Self-aligned insulated film for high-k metal gate device
- Patent number 10,388,531
- Issue date Aug 20, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jin-Aun Ng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Scan output flip-flops
- Patent number 10,361,686
- Issue date Jul 23, 2019
- Mediatek Inc.
- Min-Hang Hsieh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for reading RRAM cell
- Patent number 10,311,952
- Issue date Jun 4, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Chin-Chieh Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit
- Patent number 10,297,587
- Issue date May 21, 2019
- Mediatek Inc.
- Jen-Hang Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device including memory and logic circuit having FETs...
- Patent number 10,249,756
- Issue date Apr 2, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd
- Kuo-Chi Tu
- G11 - INFORMATION STORAGE
Information Patent Grant
Routing message delivery method applicable to network node and netw...
- Patent number 10,243,832
- Issue date Mar 26, 2019
- Industrial Technology Research Institute
- Hsien-Wen Chang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method for performing positioning operation and associated electron...
- Patent number 10,171,948
- Issue date Jan 1, 2019
- Mediatek Inc.
- Po-Yu Chen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND SYSTEM FOR AUTOMATICALLY MEASURING HANDOVER PERFORMANCE...
- Publication number 20240064590
- Publication date Feb 22, 2024
- Alpha Networks Inc.
- Shih-Fang Ao
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method for Estimating Distribution of Wireless Signal Strength, Sel...
- Publication number 20240048255
- Publication date Feb 8, 2024
- Alpha Networks Inc.
- CHIA-SHUO YEH
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
BUFFER CIRCUITS AND SEMICONDUCTOR STRUCTURES THEREOF
- Publication number 20230308099
- Publication date Sep 28, 2023
- MEDIATEK INC.
- Hao-Hsiang YU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT DEVICE AND CHIP DEVICE
- Publication number 20230238958
- Publication date Jul 27, 2023
- MEDIATEK INC.
- Bo-Ren LUNG
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
REGISTER WITH DATA RETENTION
- Publication number 20230170881
- Publication date Jun 1, 2023
- MEDIATEK INC.
- Wei-Min Hsu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ULTRA-RELIABLE AND LOW LATENCY COMMUNICATIONS LOCAL BREAKOUT METHOD...
- Publication number 20220345361
- Publication date Oct 27, 2022
- WISTRON NEWEB CORPORATION
- JEN-SHUN YANG
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
RESOURCE MANAGEMENT SYSTEM AND RESOURCE MANAGEMENT METHOD
- Publication number 20220141140
- Publication date May 5, 2022
- WISTRON NEWEB CORPORATION
- JEN-SHUN YANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LEVEL CONVERTING ENABLE LATCH
- Publication number 20220103175
- Publication date Mar 31, 2022
- MEDIATEK INC.
- Wei-Min Hsu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD FOR FORMING A FLAT BOTTOM ELECTRODE VIA (BEVA) TOP SURFACE F...
- Publication number 20220093849
- Publication date Mar 24, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hsia-Wei Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING A FLAT BOTTOM ELECTRODE VIA (BEVA) TOP SURFACE F...
- Publication number 20220085280
- Publication date Mar 17, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hsia-Wei Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECT LANDING METHOD FOR RRAM TECHNOLOGY
- Publication number 20210366988
- Publication date Nov 25, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hsia-Wei Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESSING CIRCUIT USING DELAY ELEMENT COUPLED BETWEEN CONTROL TERM...
- Publication number 20210297066
- Publication date Sep 23, 2021
- MEDIATEK INC.
- Jen-Hang YANG
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
STEP HEIGHT MITIGATION IN RESISTIVE RANDOM ACCESS MEMORY STRUCTURES
- Publication number 20210280783
- Publication date Sep 9, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Wei-Ming Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STEP HEIGHT MITIGATION IN RESISTIVE RANDOM ACCESS MEMORY STRUCTURES
- Publication number 20200373487
- Publication date Nov 26, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Wei-Ming Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING A FLAT BOTTOM ELECTRODE VIA (BEVA) TOP SURFACE F...
- Publication number 20200357981
- Publication date Nov 12, 2020
- Taiwan Semiconductor Manufacturing Co., LTD
- Hsia-Wei Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
- Publication number 20200357928
- Publication date Nov 12, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Kuo-Chi TU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECT LANDING METHOD FOR RRAM TECHNOLOGY
- Publication number 20200098828
- Publication date Mar 26, 2020
- Taiwan Semiconductor Manufacturing Co., LTD
- Hsia-Wei Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FULL ADDER CIRCUITS WITH REDUCED DELAY
- Publication number 20200065065
- Publication date Feb 27, 2020
- MEDIATEK INC.
- Ying-Chun WEI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERCONNECT LANDING METHOD FOR RRAM TECHNOLOGY
- Publication number 20200020745
- Publication date Jan 16, 2020
- Taiwan Semiconductor Manufacturing Co., LTD
- Hsia-Wei Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING A FLAT BOTTOM ELECTRODE VIA (BEVA) TOP SURFACE F...
- Publication number 20190386204
- Publication date Dec 19, 2019
- Taiwan Semiconductor Manufacturing Co., LTD
- Hsia-Wei Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Self-Aligned Insulated Film for High-K Metal Gate Device
- Publication number 20190341263
- Publication date Nov 7, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jin-Aun Ng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS FOR READING RRAM CELL
- Publication number 20190272873
- Publication date Sep 5, 2019
- Taiwan Semiconductor Manufacturing Co., LTD
- Chin-Chieh Yang
- G11 - INFORMATION STORAGE
Information Patent Application
WIRELESS COMMUNICATION METHOD AND COMMUNICATION TERMINAL DEVICE USI...
- Publication number 20190173614
- Publication date Jun 6, 2019
- Industrial Technology Research Institute
- Tze-Jie TAN
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
- Publication number 20190103493
- Publication date Apr 4, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Kuo-Chi Tu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING A FLAT BOTTOM ELECTRODE VIA (BEVA) TOP SURFACE F...
- Publication number 20190058109
- Publication date Feb 21, 2019
- Taiwan Semiconductor Manufacturing Co., LTD
- Hsia-Wei Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECT LANDING METHOD FOR RRAM TECHNOLOGY
- Publication number 20180374901
- Publication date Dec 27, 2018
- Taiwan Semiconductor Manufacturing Co., LTD
- Hsia-Wei Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SCAN OUTPUT FLIP-FLOPS
- Publication number 20180375500
- Publication date Dec 27, 2018
- MEDIATEK INC.
- Min-Hang HSIEH
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
STEP HEIGHT REDUCTION OF MEMORY ELEMENT
- Publication number 20180351099
- Publication date Dec 6, 2018
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Jen-Sheng YANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOCAL EDGE CLOUDLET MANAGER, EDGE CLOUDLET SYSTEM AND CONTROLLING M...
- Publication number 20180310292
- Publication date Oct 25, 2018
- Industrial Technology Research Institute
- Jen-Shun Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR READING RRAM CELL
- Publication number 20180218770
- Publication date Aug 2, 2018
- Taiwan Semiconductor Manufacturing Co., LTD
- Chin-Chieh Yang
- G11 - INFORMATION STORAGE

Jen-Tzu YANG

Person

Patents Grantslast 30 patents

Register with data retention

Interconnect landing method for RRAM technology

Flat bottom electrode via (BEVA) top surface for memory

Ultra-reliable and low latency communications local breakout method...

Flat bottom electrode via (BEVA) top surface for memory

Step height mitigation in resistive random access memory structures

Resource management system and resource management method

Level converting enable latch

Processing circuit using delay element coupled between control term...

Method for forming a flat bottom electrode via (BEVA) top surface f...

Interconnect landing method for RRAM technology

Self-aligned insulated film for high-K metal gate device

Step height mitigation in resistive random access memory structures

Semiconductor device and manufacturing method thereof

Interconnect landing method for RRAM technology

Method and apparatus for reading RRAM cell

Method for forming a flat bottom electrode via (BEVA) top surface f...

Semiconductor device and manufacturing method thereof

Full adder circuits with reduced delay

Method for forming a flat bottom electrode via (BEVA) top surface f...

Interconnect landing method for RRAM technology

Cell layout utilizing boundary cell with mixed poly pitch within in...

Method and system of device-to-device tunnel establishment between...

Self-aligned insulated film for high-k metal gate device

Scan output flip-flops

Method and apparatus for reading RRAM cell

Integrated circuit

Semiconductor device including memory and logic circuit having FETs...

Routing message delivery method applicable to network node and netw...

Method for performing positioning operation and associated electron...

Patents Applicationslast 30 patents

METHOD AND SYSTEM FOR AUTOMATICALLY MEASURING HANDOVER PERFORMANCE...

Method for Estimating Distribution of Wireless Signal Strength, Sel...

BUFFER CIRCUITS AND SEMICONDUCTOR STRUCTURES THEREOF

INTEGRATED CIRCUIT DEVICE AND CHIP DEVICE

REGISTER WITH DATA RETENTION

ULTRA-RELIABLE AND LOW LATENCY COMMUNICATIONS LOCAL BREAKOUT METHOD...

RESOURCE MANAGEMENT SYSTEM AND RESOURCE MANAGEMENT METHOD

LEVEL CONVERTING ENABLE LATCH

METHOD FOR FORMING A FLAT BOTTOM ELECTRODE VIA (BEVA) TOP SURFACE F...

METHOD FOR FORMING A FLAT BOTTOM ELECTRODE VIA (BEVA) TOP SURFACE F...

INTERCONNECT LANDING METHOD FOR RRAM TECHNOLOGY

PROCESSING CIRCUIT USING DELAY ELEMENT COUPLED BETWEEN CONTROL TERM...

STEP HEIGHT MITIGATION IN RESISTIVE RANDOM ACCESS MEMORY STRUCTURES

STEP HEIGHT MITIGATION IN RESISTIVE RANDOM ACCESS MEMORY STRUCTURES

METHOD FOR FORMING A FLAT BOTTOM ELECTRODE VIA (BEVA) TOP SURFACE F...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

INTERCONNECT LANDING METHOD FOR RRAM TECHNOLOGY

FULL ADDER CIRCUITS WITH REDUCED DELAY

INTERCONNECT LANDING METHOD FOR RRAM TECHNOLOGY

METHOD FOR FORMING A FLAT BOTTOM ELECTRODE VIA (BEVA) TOP SURFACE F...

Self-Aligned Insulated Film for High-K Metal Gate Device

METHOD AND APPARATUS FOR READING RRAM CELL

WIRELESS COMMUNICATION METHOD AND COMMUNICATION TERMINAL DEVICE USI...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

METHOD FOR FORMING A FLAT BOTTOM ELECTRODE VIA (BEVA) TOP SURFACE F...

INTERCONNECT LANDING METHOD FOR RRAM TECHNOLOGY

SCAN OUTPUT FLIP-FLOPS

STEP HEIGHT REDUCTION OF MEMORY ELEMENT

LOCAL EDGE CLOUDLET MANAGER, EDGE CLOUDLET SYSTEM AND CONTROLLING M...

METHOD AND APPARATUS FOR READING RRAM CELL