Jeong Yeol Choi

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
System with logic and embedded MIM capacitor
- Patent number 8,587,046
- Issue date Nov 19, 2013
- MoSys, Inc.
- Jeong Y. Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a MIM capacitor
- Patent number 8,460,995
- Issue date Jun 11, 2013
- MoSys, Inc.
- Jeong Y. Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Embedded DRAM with multiple gate oxide thicknesses
- Patent number 8,361,863
- Issue date Jan 29, 2013
- MoSys, Inc.
- Jeong Y. Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for restoring data in a non-volatile memory
- Patent number 8,238,169
- Issue date Aug 7, 2012
- MoSys, Inc.
- Jeong Y. Choi
- G11 - INFORMATION STORAGE
Information Patent Grant
Embedded DRAM with bias-independent capacitance
- Patent number 7,929,359
- Issue date Apr 19, 2011
- MoSys, Inc.
- Jae Hong Jeong
- G11 - INFORMATION STORAGE
Information Patent Grant
Data restoration method for a non-volatile memory
- Patent number 7,894,270
- Issue date Feb 22, 2011
- MoSys, Inc.
- Jeong Y. Choi
- G11 - INFORMATION STORAGE
Information Patent Grant
Hot carrier circuit reliability simulation
- Patent number 7,835,890
- Issue date Nov 16, 2010
- Cadence Design Systems, Inc.
- Lifeng Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hot-carrier device degradation modeling and extraction methodologies
- Patent number 7,567,891
- Issue date Jul 28, 2009
- Cadence Design Systems, Inc.
- Zhihong Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for forming photomask having test patterns in blading areas
- Patent number 7,378,289
- Issue date May 27, 2008
- Integrated Device Technology, Inc.
- Zhijian Ma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hot carrier circuit reliability simulation
- Patent number 7,292,968
- Issue date Nov 6, 2007
- Cadence Design Systems, Inc.
- Lifeng Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hot-carrier reliability design rule checker
- Patent number 7,219,045
- Issue date May 15, 2007
- Cadence Design Systems, Inc.
- Lifeng Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for forming hybrid device gates
- Patent number 7,125,775
- Issue date Oct 24, 2006
- Integrated Device Technology, Inc.
- Kuilong Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods, apparatus and computer program products for modeling integ...
- Patent number 6,898,561
- Issue date May 24, 2005
- Integrated Device Technology, Inc.
- Chunbo Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
SRAM system having very lightly doped SRAM load transistors for imp...
- Patent number 6,894,356
- Issue date May 17, 2005
- Integrated Device Technology, Inc.
- Jeong Yeol Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Compact ternary content addressable memory cell
- Patent number 6,496,399
- Issue date Dec 17, 2002
- Integrated Device Technology, Inc.
- Jeong Yeol Choi
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of forming an oxide layer
- Patent number 6,407,008
- Issue date Jun 18, 2002
- Integrated Device Technology, Inc.
- Yingbo Jia
- C30 - CRYSTAL GROWTH
Information Patent Grant
Ion implantation for scalability of isolation in an integrated circuit
- Patent number 6,258,693
- Issue date Jul 10, 2001
- Integrated Device Technology, Inc.
- Jeong Y. Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Identical gate conductivity type static random access memory cell
- Patent number 6,191,460
- Issue date Feb 20, 2001
- Integrated Device Technology, Inc.
- Jeong Y. Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming gate oxides of different thicknesses
- Patent number 6,165,918
- Issue date Dec 26, 2000
- Integrated Device Technology, Inc.
- James Yingbo Jia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS structure having a gate without spacers
- Patent number 6,127,710
- Issue date Oct 3, 2000
- Integrated Device Technology, Inc.
- Jeong Yeol Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of improving the reliability of low-voltage programmable ant...
- Patent number 6,103,555
- Issue date Aug 15, 2000
- Integrated Device Technology, Inc.
- Jeong Yeol Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming isolation regions subsequent to gate formation a...
- Patent number 6,069,054
- Issue date May 30, 2000
- Integrated Device Technology, Inc.
- Jeong Y. Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Mosfet with raised source and drain regions
- Patent number 6,063,676
- Issue date May 16, 2000
- Integrated Device Technology, Inc.
- Jeong Yeol Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density MOSFET with raised source and drain regions
- Patent number 6,043,129
- Issue date Mar 28, 2000
- Integrated Device Technology, Inc.
- Jeong Yeol Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for improving latch-up immunity and interwell isolation in a...
- Patent number 6,017,785
- Issue date Jan 25, 2000
- Integrated Device Technology, Inc.
- Chung-Chyung Han
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Efficient method for fabricating P-wells and N-wells
- Patent number 5,926,704
- Issue date Jul 20, 1999
- Integrated Device Technology, Inc.
- Jeong Y. Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing a BiCMOS integrated circuit fully integrate...
- Patent number 5,888,861
- Issue date Mar 30, 1999
- Integrated Device Technology, Inc.
- Chung-Jen Chien
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS process forming wells after gate formation
- Patent number 5,830,789
- Issue date Nov 3, 1998
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure for improving latch-up immunity and interwell isolation i...
- Patent number 5,831,313
- Issue date Nov 3, 1998
- Integrated Device Technology, Inc.
- Chung-Chyung Han
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure for controlling threshold voltage of MOSFET
- Patent number 5,793,088
- Issue date Aug 11, 1998
- Integrated Device Technology, Inc.
- Jeong Yeol Choi
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Non-Volatile Memory System with Modified Memory Cells
- Publication number 20120056257
- Publication date Mar 8, 2012
- MoSys, Inc.
- Jeong Y. Choi
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM WITH LOGIC AND EMBEDDED MIM CAPACITOR
- Publication number 20120025285
- Publication date Feb 2, 2012
- MoSys, Inc.
- Jeong Y. Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming a MIM capacitor
- Publication number 20120025347
- Publication date Feb 2, 2012
- MoSys, Inc.
- Jeong Y. Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Reliability Protection for Non-Volatile Memories
- Publication number 20110216596
- Publication date Sep 8, 2011
- MOSYS, INC.
- Jeong Y. Choi
- G11 - INFORMATION STORAGE
Information Patent Application
Method and Apparatus for Restoring Data in a Non-Volatile Memory
- Publication number 20110141812
- Publication date Jun 16, 2011
- MoSys, Inc.
- Jeong Y. Choi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Data restoration method for a non-volatile memory
- Publication number 20100202203
- Publication date Aug 12, 2010
- MOSYS, INC.
- Jeong Y. Choi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Double Polysilicon Process for Non-Volatile Memory
- Publication number 20100140680
- Publication date Jun 10, 2010
- MOSYS, INC.
- Jeong Y. Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Embedded DRAM with bias-independent capacitance
- Publication number 20100118596
- Publication date May 13, 2010
- MOSYS, INC.
- Jae Hong Jeong
- G11 - INFORMATION STORAGE
Information Patent Application
Embedded DRAM with multiple gate oxide thicknesses
- Publication number 20100120213
- Publication date May 13, 2010
- MOSYS, INC.
- Jeong Y. Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Hot-Carrier Device Degradation Modeling and Extraction Methodologies
- Publication number 20090299716
- Publication date Dec 3, 2009
- Zhihong Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hot Carrier Circuit Reliability Simulation
- Publication number 20080027699
- Publication date Jan 31, 2008
- Lifeng Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SRAM System having very lightly doped SRAM load transistors for imp...
- Publication number 20030173625
- Publication date Sep 18, 2003
- Integrated Device Technology, Inc.
- Jeong Yeol Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Hot carrier circuit reliability simulation
- Publication number 20030055621
- Publication date Mar 20, 2003
- Lifeng Wu
- G06 - COMPUTING CALCULATING COUNTING

Jeong Yeol Choi

Person

Patents Grantslast 30 patents

System with logic and embedded MIM capacitor

Method of forming a MIM capacitor

Embedded DRAM with multiple gate oxide thicknesses

Method and apparatus for restoring data in a non-volatile memory

Embedded DRAM with bias-independent capacitance

Data restoration method for a non-volatile memory

Hot carrier circuit reliability simulation

Hot-carrier device degradation modeling and extraction methodologies

Method for forming photomask having test patterns in blading areas

Hot carrier circuit reliability simulation

Hot-carrier reliability design rule checker

Method for forming hybrid device gates

Methods, apparatus and computer program products for modeling integ...

SRAM system having very lightly doped SRAM load transistors for imp...

Compact ternary content addressable memory cell

Method of forming an oxide layer

Ion implantation for scalability of isolation in an integrated circuit

Identical gate conductivity type static random access memory cell

Method for forming gate oxides of different thicknesses

CMOS structure having a gate without spacers

Method of improving the reliability of low-voltage programmable ant...

Method for forming isolation regions subsequent to gate formation a...

Mosfet with raised source and drain regions

High density MOSFET with raised source and drain regions

Method for improving latch-up immunity and interwell isolation in a...

Efficient method for fabricating P-wells and N-wells

Method of manufacturing a BiCMOS integrated circuit fully integrate...

CMOS process forming wells after gate formation

Structure for improving latch-up immunity and interwell isolation i...

Structure for controlling threshold voltage of MOSFET

Patents Applicationslast 30 patents

Non-Volatile Memory System with Modified Memory Cells

SYSTEM WITH LOGIC AND EMBEDDED MIM CAPACITOR

Method of forming a MIM capacitor

Reliability Protection for Non-Volatile Memories

Method and Apparatus for Restoring Data in a Non-Volatile Memory

Data restoration method for a non-volatile memory

Double Polysilicon Process for Non-Volatile Memory

Embedded DRAM with bias-independent capacitance

Embedded DRAM with multiple gate oxide thicknesses

Hot-Carrier Device Degradation Modeling and Extraction Methodologies

Hot Carrier Circuit Reliability Simulation

SRAM System having very lightly doped SRAM load transistors for imp...

Hot carrier circuit reliability simulation