Jerimy C. Nelson

Person

Ft. Collins, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Routing vias in a substrate from bypass capacitor pads
- Patent number 7,326,860
- Issue date Feb 5, 2008
- Hewlett-Packard Development Company, L.P.
- Jerimy Nelson
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Routing power and ground vias in a substrate
- Patent number 7,327,583
- Issue date Feb 5, 2008
- Hewlett-Packard Development Company, L.P.
- Jerimy Nelson
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
System and method for evaluating power and ground vias in a package...
- Patent number 7,272,806
- Issue date Sep 18, 2007
- Hewlett-Packard Development Company, L.P.
- Mark D. Frank
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for integrating subcircuit models in an integrate...
- Patent number 7,143,022
- Issue date Nov 28, 2006
- Hewlett-Packard Development Company, L.P.
- Yong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for generating node level bypass capacitor models
- Patent number 7,143,389
- Issue date Nov 28, 2006
- Hewlett-Packard Development Company, L.P.
- Yong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for determining signal coupling coefficients for...
- Patent number 7,137,088
- Issue date Nov 14, 2006
- Hewlett-Packard Development Company, L.P.
- Mark D. Frank
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for evaluating signal coupling between differenti...
- Patent number 7,117,464
- Issue date Oct 3, 2006
- Hewlett-Packard Development Company, L.P.
- Mark D. Frank
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing differential signal lines in a substrate
- Patent number 7,078,812
- Issue date Jul 18, 2006
- Hewlett-Packard Development Company, L.P.
- Mark D. Frank
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Routing vias in a substrate from bypass capacitor pads
- Patent number 7,075,185
- Issue date Jul 11, 2006
- Hewlett-Packard Development Company, L.P.
- Jerimy Nelson
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
System and method for populating a computer-aided design program's...
- Patent number 7,069,095
- Issue date Jun 27, 2006
- Hewlett-Packard Development Company, L.P.
- Jerimy Nelson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for evaluating signal deviations in a package design
- Patent number 7,055,124
- Issue date May 30, 2006
- Hewlett-Packard Development Company, L.P.
- Mark D. Frank
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Differential line pair impedance adjustment tool
- Patent number 6,983,433
- Issue date Jan 3, 2006
- Hewlett-Packard Development Company, L.P.
- Mark D. Frank
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Differential via pair impedance adjustment tool
- Patent number 6,983,434
- Issue date Jan 3, 2006
- Hewlett-Packard Development Company, L.P.
- Mark D. Frank
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Signal via impedance verification tool
- Patent number 6,976,233
- Issue date Dec 13, 2005
- Hewlett-Packard Development Company, L.P.
- Mark D. Frank
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Signal line impedance adjustment tool
- Patent number 6,971,077
- Issue date Nov 29, 2005
- Hewlett-Packard Development Company, L.P.
- Mark D. Frank
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Differential line pair impedance verification tool
- Patent number 6,968,522
- Issue date Nov 22, 2005
- Hewlett-Packard Development Company, L.P.
- Mark D. Frank
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for evaluating signal trace discontinuities in a...
- Patent number 6,938,230
- Issue date Aug 30, 2005
- Hewlett-Packard Development Company, L.P.
- Mark D. Frank
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verifying proximity of ground vias to signal vias in an integrated...
- Patent number 6,922,822
- Issue date Jul 26, 2005
- Hewlett-Packard Development Company, L.P.
- Mark D. Frank
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for evaluating vias per pad in a package design
- Patent number 6,907,589
- Issue date Jun 14, 2005
- Hewlett-Packard Development Company, L.P.
- Mark D. Frank
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Differential via pair impedance verification tool
- Patent number 6,889,367
- Issue date May 3, 2005
- Hewlett-Packard Development Company, L.P.
- Mark D. Frank
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Signal line impedance verification tool
- Patent number 6,859,915
- Issue date Feb 22, 2005
- Hewlett-Packard Development Company, L.P.
- Mark D. Frank
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Signal via impedance adjustment tool
- Patent number 6,845,492
- Issue date Jan 18, 2005
- Hewlett-Packard Development Company, L.P.
- Mark D. Frank
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inter-signal proximity verification in an integrated circuit
- Patent number 6,807,657
- Issue date Oct 19, 2004
- Hewlett-Packard Development Company, L.P.
- Mark D. Frank
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verifying proximity of ground metal to signal traces in an integrat...
- Patent number 6,769,102
- Issue date Jul 27, 2004
- Hewlett-Packard Development Company
- Mark D. Frank
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM AND METHOD FOR EVALUATING SIGNAL COUPLING BETWEEN DIFFERENTI...
- Publication number 20060236276
- Publication date Oct 19, 2006
- Mark D. Frank
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Routing vias in a substrate from bypass capacitor pads
- Publication number 20060225916
- Publication date Oct 12, 2006
- Jerimy Nelson
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Routing vias in a substrate from bypass capacitor pads
- Publication number 20060055049
- Publication date Mar 16, 2006
- Jerimy Nelson
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Routing power and ground vias in a substrate
- Publication number 20060055022
- Publication date Mar 16, 2006
- Jerimy Nelson
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Routing differential signal lines in a substrate
- Publication number 20060043537
- Publication date Mar 2, 2006
- Mark D. Frank
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Systems and methods for generating node level bypass capacitor models
- Publication number 20060026542
- Publication date Feb 2, 2006
- Yong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for determining signal coupling in a circuit design
- Publication number 20050251769
- Publication date Nov 10, 2005
- Mark D. Frank
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for determining signal coupling coefficients for...
- Publication number 20050249479
- Publication date Nov 10, 2005
- Mark D. Frank
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for determining signal coupling coefficients for...
- Publication number 20050251770
- Publication date Nov 10, 2005
- Mark D. Frank
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Differential trace pair coupling verification tool
- Publication number 20050246672
- Publication date Nov 3, 2005
- Karl J. Bois
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Differential via pair coupling verification tool
- Publication number 20050246670
- Publication date Nov 3, 2005
- Karl J. Bois
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for determining worst case coupling within a d...
- Publication number 20050246671
- Publication date Nov 3, 2005
- Karl J. Bois
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for evaluating signal trace discontinuities in a...
- Publication number 20050223348
- Publication date Oct 6, 2005
- Mark D. Frank
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for maintaining homogeneity between a model in a...
- Publication number 20050197807
- Publication date Sep 8, 2005
- Jerimy Nelson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for populating a computer-aided design program's...
- Publication number 20050125747
- Publication date Jun 9, 2005
- Jerimy Nelson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for evaluating power and ground vias in a package...
- Publication number 20040162715
- Publication date Aug 19, 2004
- Mark D. Frank
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for evaluating signal coupling between vias in a...
- Publication number 20040163056
- Publication date Aug 19, 2004
- Mark D. Frank
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for evaluating signal deviations in a package design
- Publication number 20040162714
- Publication date Aug 19, 2004
- Mark D. Frank
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for evaluating vias per pad in a package design
- Publication number 20040163054
- Publication date Aug 19, 2004
- Mark D. Frank
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for evaluating signal trace discontinuities in a...
- Publication number 20040163057
- Publication date Aug 19, 2004
- Mark D. Frank
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for evaluating signal coupling between differenti...
- Publication number 20040163058
- Publication date Aug 19, 2004
- Mark D. Frank
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Verifying proximity of ground metal to signal traces in an integrat...
- Publication number 20040015795
- Publication date Jan 22, 2004
- Mark D. Frank
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Inter-signal proximity verification in an integrated circuit
- Publication number 20040015806
- Publication date Jan 22, 2004
- Mark D. Frank
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Verifying proximity of ground vias to signal vias in an integrated...
- Publication number 20040015796
- Publication date Jan 22, 2004
- Mark D. Frank
- G06 - COMPUTING CALCULATING COUNTING

Jerimy C. Nelson

Person

Patents Grantslast 30 patents

Routing vias in a substrate from bypass capacitor pads

Routing power and ground vias in a substrate

System and method for evaluating power and ground vias in a package...

System and method for integrating subcircuit models in an integrate...

Systems and methods for generating node level bypass capacitor models

System and method for determining signal coupling coefficients for...

System and method for evaluating signal coupling between differenti...

Routing differential signal lines in a substrate

Routing vias in a substrate from bypass capacitor pads

System and method for populating a computer-aided design program's...

System and method for evaluating signal deviations in a package design

Differential line pair impedance adjustment tool

Differential via pair impedance adjustment tool

Signal via impedance verification tool

Signal line impedance adjustment tool

Differential line pair impedance verification tool

System and method for evaluating signal trace discontinuities in a...

Verifying proximity of ground vias to signal vias in an integrated...

System and method for evaluating vias per pad in a package design

Differential via pair impedance verification tool

Signal line impedance verification tool

Signal via impedance adjustment tool

Inter-signal proximity verification in an integrated circuit

Verifying proximity of ground metal to signal traces in an integrat...

Patents Applicationslast 30 patents

SYSTEM AND METHOD FOR EVALUATING SIGNAL COUPLING BETWEEN DIFFERENTI...

Routing vias in a substrate from bypass capacitor pads

Routing vias in a substrate from bypass capacitor pads

Routing power and ground vias in a substrate

Routing differential signal lines in a substrate

Systems and methods for generating node level bypass capacitor models

System and method for determining signal coupling in a circuit design

System and method for determining signal coupling coefficients for...

System and method for determining signal coupling coefficients for...

Differential trace pair coupling verification tool

Differential via pair coupling verification tool

Method and apparatus for determining worst case coupling within a d...

System and method for evaluating signal trace discontinuities in a...

System and method for maintaining homogeneity between a model in a...

System and method for populating a computer-aided design program's...

System and method for evaluating power and ground vias in a package...

System and method for evaluating signal coupling between vias in a...

System and method for evaluating signal deviations in a package design

System and method for evaluating vias per pad in a package design

System and method for evaluating signal trace discontinuities in a...

System and method for evaluating signal coupling between differenti...

Verifying proximity of ground metal to signal traces in an integrat...

Inter-signal proximity verification in an integrated circuit

Verifying proximity of ground vias to signal vias in an integrated...