Jesus Mennen Belonio JR.

Person

Neubiberg, DE

People

Patents Grantslast 30 patents

Information Patent Grant
3D MIS-FO hybrid for embedded inductor package structure
- Patent number 12,205,750
- Issue date Jan 21, 2025
- Dialog Semiconductor (UK) Limited
- Shih-Wen Tang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Embedded resistor-capacitor film for fan out wafer level packaging
- Patent number 12,100,674
- Issue date Sep 24, 2024
- Dialog Semiconductor (UK) Limited
- Ernesto Gutierrez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Single side modular 3D stack up SiP with mold cavity
- Patent number 11,621,218
- Issue date Apr 4, 2023
- Dialog Semiconductor (UK) Limited
- Shih-Wen Tang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pillared cavity down MIS-SiP
- Patent number 11,532,489
- Issue date Dec 20, 2022
- Dialog Semiconductor (UK) Limited
- Ernesto Gutierrez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Very thin embedded trace substrate-system in package (SIP)
- Patent number 11,309,255
- Issue date Apr 19, 2022
- Dialog Semiconductor (UK) Limited
- Jesus Mennen Belonio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated type MIS substrate for thin double side SIP package
- Patent number 11,251,132
- Issue date Feb 15, 2022
- Dialog Semiconductor (UK) Limited
- Chehan Jerry Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Embedded resistor-capacitor film for fan out wafer level packaging
- Patent number 11,239,185
- Issue date Feb 1, 2022
- Dialog Semiconductor (UK) Limited
- Ernesto Gutierrez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Modular WLCSP die daisy chain design for multiple die sizes
- Patent number 11,158,551
- Issue date Oct 26, 2021
- Dialog Semiconductor (UK) Limited
- Duncan Barclay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level chip scale package structure
- Patent number 11,114,359
- Issue date Sep 7, 2021
- Dialog Semiconductor (UK) Limited
- Jesus Mennen Belonio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level molded PPGA (pad post grid array) for low cost package
- Patent number 11,094,669
- Issue date Aug 17, 2021
- Dialog Semiconductor B.V.
- Shou Cheng Eric Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pillared cavity down MIS-SIP
- Patent number 11,075,167
- Issue date Jul 27, 2021
- Dialog Semiconductor (UK) Limited
- Ernesto Gutierrez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package and a method for forming a wafer level c...
- Patent number 10,727,174
- Issue date Jul 28, 2020
- Dialog Semiconductor (UK) Limited
- Jesus Mennen Belonio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Very thin embedded trace substrate-system in package (SIP)
- Patent number 10,636,742
- Issue date Apr 28, 2020
- Dialog Semiconductor (US) Limited
- Jesus Mennen Belonio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System in package (SIP)
- Patent number 10,629,507
- Issue date Apr 21, 2020
- Dialog Semiconductor (UK) Limited
- Che-Han Jerry Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stress relief solutions on WLCSP large/bulk copper plane design
- Patent number 10,083,926
- Issue date Sep 25, 2018
- Dialog Semiconductor (UK) Limited
- Ian Kent
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
3D MIS-FO Hybrid for Embedded Inductor Package Structure
- Publication number 20230170131
- Publication date Jun 1, 2023
- Dialog Semiconductor (UK) Limited
- Shih-Wen Tang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Embedded Resistor-Capacitor Film for Fan Out Wafer Level Packaging
- Publication number 20220139850
- Publication date May 5, 2022
- Dialog Semiconductor (UK) Limited
- Ernesto Gutierrez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Pillared Cavity Down MIS-SIP
- Publication number 20210305167
- Publication date Sep 30, 2021
- Dialog Semiconductor (UK) Limited
- Ernesto Gutierrez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Modular WLCSP Die Daisy Chain Design for Multiple Die Sizes
- Publication number 20210210396
- Publication date Jul 8, 2021
- Dialog Semiconductor (UK) Limited
- Duncan Barclay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Pillared Cavity Down MIS-SIP
- Publication number 20200251350
- Publication date Aug 6, 2020
- Dialog Semiconductor (UK) Limited
- Ernesto Gutierrez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Very Thin Embedded Trace Substrate-System in Package (SIP)
- Publication number 20200227356
- Publication date Jul 16, 2020
- Dialog Semiconductor (UK) Limited
- Jesus Mennen Belonio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wafer Level Chip Scale Package Structure
- Publication number 20200091026
- Publication date Mar 19, 2020
- Dialog Semiconductor (UK) Limited
- Jesus Mennen Belonio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Circuit Package and a method for Forming a Wafer Level C...
- Publication number 20200091051
- Publication date Mar 19, 2020
- Dialog Semiconductor (UK) Limited
- Jesus Mennen Belonio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wafer Level Molded PPGA (Pad Post Grid Array) for Low Cost Package
- Publication number 20190326254
- Publication date Oct 24, 2019
- Dialog Semiconductor B.V.
- Shou Cheng Eric Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wafer Level UGA (UBM Grid Array) & PGA (Pad Grid Array) for Low Cos...
- Publication number 20190267342
- Publication date Aug 29, 2019
- Dialog Semiconductor B.V.
- Shou Cheng Eric Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wafer Level Molded PPGA (Pad Post Grid Array) for Low Cost Package
- Publication number 20190181115
- Publication date Jun 13, 2019
- Dialog Semiconductor (UK) Limited
- Shou Cheng Eric Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Embedded Resistor-Capacitor Film for Fan Out Wafer Level Packaging
- Publication number 20190139911
- Publication date May 9, 2019
- Dialog Semiconductor (UK) Limited
- Ernesto Gutierrez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Very Thin Embedded Trace Substrate-System in Package (SIP)
- Publication number 20190096815
- Publication date Mar 28, 2019
- Dialog Semiconductor (UK) Limited
- Jesus Mennen Belonio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WFCQFN (Very-Very Thin Flip Chip Quad Flat No Lead) with Embedded C...
- Publication number 20180025965
- Publication date Jan 25, 2018
- Dialog Semiconductor (UK) Limited
- Baltazar Canete
- H01 - BASIC ELECTRIC ELEMENTS

Jesus Mennen Belonio JR.

Person

Patents Grantslast 30 patents

3D MIS-FO hybrid for embedded inductor package structure

Embedded resistor-capacitor film for fan out wafer level packaging

Single side modular 3D stack up SiP with mold cavity

Pillared cavity down MIS-SiP

Very thin embedded trace substrate-system in package (SIP)

Integrated type MIS substrate for thin double side SIP package

Embedded resistor-capacitor film for fan out wafer level packaging

Modular WLCSP die daisy chain design for multiple die sizes

Wafer level chip scale package structure

Wafer level molded PPGA (pad post grid array) for low cost package

Pillared cavity down MIS-SIP

Integrated circuit package and a method for forming a wafer level c...

Very thin embedded trace substrate-system in package (SIP)

System in package (SIP)

Stress relief solutions on WLCSP large/bulk copper plane design

Patents Applicationslast 30 patents

3D MIS-FO Hybrid for Embedded Inductor Package Structure

Embedded Resistor-Capacitor Film for Fan Out Wafer Level Packaging

Pillared Cavity Down MIS-SIP

Modular WLCSP Die Daisy Chain Design for Multiple Die Sizes

Pillared Cavity Down MIS-SIP

Very Thin Embedded Trace Substrate-System in Package (SIP)

Wafer Level Chip Scale Package Structure

Integrated Circuit Package and a method for Forming a Wafer Level C...

Wafer Level Molded PPGA (Pad Post Grid Array) for Low Cost Package

Wafer Level UGA (UBM Grid Array) & PGA (Pad Grid Array) for Low Cos...

Wafer Level Molded PPGA (Pad Post Grid Array) for Low Cost Package

Embedded Resistor-Capacitor Film for Fan Out Wafer Level Packaging

Very Thin Embedded Trace Substrate-System in Package (SIP)

WFCQFN (Very-Very Thin Flip Chip Quad Flat No Lead) with Embedded C...