Ji Zhao

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Phase-locked loop systems and methods
- Patent number 7,439,783
- Issue date Oct 21, 2008
- Lattice Semiconductor Corporation
- Harald Weller
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital A/V transmission PHY signaling format conversion, multiplex...
- Patent number 7,397,283
- Issue date Jul 8, 2008
- Parade Technologies, Ltd.
- Jimmy Chiu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Systems and methods for reducing static phase error
- Patent number 7,382,169
- Issue date Jun 3, 2008
- Lattice Semiconductor Corporation
- Ludmil Nikolov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
SERDES with programmable I/O architecture
- Patent number 7,327,160
- Issue date Feb 5, 2008
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
SERDES with programmable I/O architecture
- Patent number 7,208,975
- Issue date Apr 24, 2007
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiple width random number generation
- Patent number 6,832,231
- Issue date Dec 14, 2004
- Lattice Semiconductor Corp.
- Xueping Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low jitter integrated phase locked loop with broad tuning range
- Patent number 6,825,733
- Issue date Nov 30, 2004
- Lattice Semiconductor Corp.
- Ming Qu
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Coupling for LC-based VCO
- Patent number 6,650,188
- Issue date Nov 18, 2003
- Lattice Semiconductor Corporation
- Edwin Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low voltage, high speed CMOS CML latch and MUX devices
- Patent number 6,614,291
- Issue date Sep 2, 2003
- Lattice Semiconductor Corp.
- Ji Zhao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Buffering for LC-based stage
- Patent number 6,525,617
- Issue date Feb 25, 2003
- Lattice Semiconductor Corporation
- Edwin Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low jitter integrated phase locked loop with broad tuning range
- Patent number 6,498,538
- Issue date Dec 24, 2002
- Lattice Semiconductor Corporation
- Ming Qu
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Coupling for LC-based VCO
- Patent number 6,492,877
- Issue date Dec 10, 2002
- Lattice Semiconductor Corporation
- Edwin Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High speed data sampling with reduced metastability
- Patent number 6,429,692
- Issue date Aug 6, 2002
- Octillion Communications, Inc.
- Edwin Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods for making VLSI capacitors and high Q VLSI inductors using...
- Patent number 6,146,958
- Issue date Nov 14, 2000
- National Semiconductor Corporation
- Ji Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
VLSI capacitors and high Q VLSI inductors using metal-filled via plugs
- Patent number 5,861,647
- Issue date Jan 19, 1999
- National Semiconductor Corporation
- Ji Zhao
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Digital A/V Transmission PHY Signaling Format Conversion, Multiplex...
- Publication number 20080079462
- Publication date Apr 3, 2008
- Parade Technologies, Ltd.
- Jimmy Chiu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Systems and methods for reducing static phase error
- Publication number 20070164798
- Publication date Jul 19, 2007
- Lattice Semiconductor Corporation
- Ludmil Nikolov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Phase-locked loop systems and methods
- Publication number 20070164799
- Publication date Jul 19, 2007
- Lattice Semiconductor Corporation
- Harald Weller
- H03 - BASIC ELECTRONIC CIRCUITRY

Person

Patents Grantslast 30 patents

Phase-locked loop systems and methods

Digital A/V transmission PHY signaling format conversion, multiplex...

Systems and methods for reducing static phase error

SERDES with programmable I/O architecture

SERDES with programmable I/O architecture

Multiple width random number generation

Low jitter integrated phase locked loop with broad tuning range

Coupling for LC-based VCO

Low voltage, high speed CMOS CML latch and MUX devices

Buffering for LC-based stage

Low jitter integrated phase locked loop with broad tuning range

Coupling for LC-based VCO

High speed data sampling with reduced metastability

Methods for making VLSI capacitors and high Q VLSI inductors using...

VLSI capacitors and high Q VLSI inductors using metal-filled via plugs

Patents Applicationslast 30 patents

Digital A/V Transmission PHY Signaling Format Conversion, Multiplex...

Systems and methods for reducing static phase error

Phase-locked loop systems and methods