Jia-Wei Yang

Person

Hsinchu, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Router and resource assignment method thereof
- Patent number 9,774,515
- Issue date Sep 26, 2017
- Wistron NeWeb Corp.
- I-Hsun Liu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Structure for an LDMOS transistor and fabrication method thereof
- Patent number 7,476,934
- Issue date Jan 13, 2009
- Vanguard International Semiconductor Corporation
- Jia-Wei Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Deep trench isolation structure of a high-voltage device and method...
- Patent number 7,242,070
- Issue date Jul 10, 2007
- Vanguard International Semiconductor Corporation
- Jia-Wei Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure for an LDMOS transistor and fabrication method for thereof
- Patent number 7,074,658
- Issue date Jul 11, 2006
- Vanguard International Semiconductor Corporatio
- Jia-Wei Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication method for a deep trench isolation structure of a high-...
- Patent number 7,041,572
- Issue date May 9, 2006
- Vanguard International Semiconductor Corporation
- Jia-Wei Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Deep trench isolation structure of a high-voltage device and method...
- Patent number 6,972,471
- Issue date Dec 6, 2005
- Vanguard International Semiconductor Corporation
- Jia-Wei Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High-voltage device process compatible with low-voltage device process
- Patent number 6,680,231
- Issue date Jan 20, 2004
- Vanguard International Semiconductor Corporation
- Jia-Wei Yang
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
ROUTER AND RESOURCE ASSIGNMENT METHOD THEREOF
- Publication number 20160029284
- Publication date Jan 28, 2016
- WISTRON NEWEB CORP.
- I-HSUN LIU
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Structure for an LDMOS transistor and fabrication method thereof
- Publication number 20060220117
- Publication date Oct 5, 2006
- Vanguard International Semiconductor Corporation
- Jia-Wei Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Deep trench isolation structure of a high-voltage device and method...
- Publication number 20060027890
- Publication date Feb 9, 2006
- Vanguard International Semiconductor Corporation
- Jia-Wei Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of reducing step height
- Publication number 20050202638
- Publication date Sep 15, 2005
- Jia-Wei Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Structure for an LDMOS transistor and fabrication method for thereof
- Publication number 20040224492
- Publication date Nov 11, 2004
- Jia-Wei Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Fabrication method for a deep trench isolation structure of a high-...
- Publication number 20040171220
- Publication date Sep 2, 2004
- VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
- Jia-Wei Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Deep trench isolation structure of a high-voltage device and method...
- Publication number 20040082140
- Publication date Apr 29, 2004
- Jia-Wei Yang
- H01 - BASIC ELECTRIC ELEMENTS

Jia-Wei Yang

Person

Patents Grantslast 30 patents

Router and resource assignment method thereof

Structure for an LDMOS transistor and fabrication method thereof

Deep trench isolation structure of a high-voltage device and method...

Structure for an LDMOS transistor and fabrication method for thereof

Fabrication method for a deep trench isolation structure of a high-...

Deep trench isolation structure of a high-voltage device and method...

High-voltage device process compatible with low-voltage device process

Patents Applicationslast 30 patents

ROUTER AND RESOURCE ASSIGNMENT METHOD THEREOF

Structure for an LDMOS transistor and fabrication method thereof

Deep trench isolation structure of a high-voltage device and method...

Method of reducing step height

Structure for an LDMOS transistor and fabrication method for thereof

Fabrication method for a deep trench isolation structure of a high-...

Deep trench isolation structure of a high-voltage device and method...