Jiann-Jeng Duh

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Sequential flow-control and FIFO memory devices having error detect...
- Patent number 7,246,300
- Issue date Jul 17, 2007
- Integrated Device Technology Inc.
- Mario Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sequential flow-control and FIFO memory devices that are depth expa...
- Patent number 7,209,983
- Issue date Apr 24, 2007
- Integrated Device Technology, Inc.
- Mario Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FIFO memory devices having write and read control circuits that sup...
- Patent number 7,158,440
- Issue date Jan 2, 2007
- Integrated Device Technology, Inc.
- Jiann-Jeng Duh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit memory devices having clock signal arbitration c...
- Patent number 7,093,047
- Issue date Aug 15, 2006
- Integrated Device Technology, Inc.
- Mario Au
- G11 - INFORMATION STORAGE
Information Patent Grant
FIFO memory devices having multi-port cache memory arrays therein t...
- Patent number 7,076,610
- Issue date Jul 11, 2006
- Integrated Device Technology, Inc.
- Mario Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fifo memory devices that support all four combinations of DDR or SD...
- Patent number 6,795,360
- Issue date Sep 21, 2004
- Integrated Device Technology, Inc.
- Jiann-Jeng Duh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FIFO memory devices that support all combinations of DDR and SDR re...
- Patent number 6,778,454
- Issue date Aug 17, 2004
- Integrated Device Technology, Inc.
- Jiann-Jeng Duh
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
FIFO memory devices having write and read control circuits that sup...
- Publication number 20050041450
- Publication date Feb 24, 2005
- Jiann-Jeng Duh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated circuit memory devices having clock signal arbitration c...
- Publication number 20050005069
- Publication date Jan 6, 2005
- Mario Au
- G11 - INFORMATION STORAGE
Information Patent Application
Sequential flow-control and FIFO memory devices that are depth expa...
- Publication number 20050005082
- Publication date Jan 6, 2005
- Mario Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FIFO memory devices having multi-port cache memory arrays therein t...
- Publication number 20040047209
- Publication date Mar 11, 2004
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Application
FIFO memory devices having multi-port cache memory arrays therein t...
- Publication number 20040019743
- Publication date Jan 29, 2004
- Mario Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FIFO memory devices that support all combinations of DDR and SDR re...
- Publication number 20030206475
- Publication date Nov 6, 2003
- Jiann-Jeng Duh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FIFO memory devices having single data rate (SDR) and dual data rat...
- Publication number 20030112685
- Publication date Jun 19, 2003
- Jiann-Jeng Duh
- G06 - COMPUTING CALCULATING COUNTING

Jiann-Jeng Duh

Person

Patents Grantslast 30 patents

Sequential flow-control and FIFO memory devices having error detect...

Sequential flow-control and FIFO memory devices that are depth expa...

FIFO memory devices having write and read control circuits that sup...

Integrated circuit memory devices having clock signal arbitration c...

FIFO memory devices having multi-port cache memory arrays therein t...

Fifo memory devices that support all four combinations of DDR or SD...

FIFO memory devices that support all combinations of DDR and SDR re...

Patents Applicationslast 30 patents

FIFO memory devices having write and read control circuits that sup...

Integrated circuit memory devices having clock signal arbitration c...

Sequential flow-control and FIFO memory devices that are depth expa...

FIFO memory devices having multi-port cache memory arrays therein t...

FIFO memory devices having multi-port cache memory arrays therein t...

FIFO memory devices that support all combinations of DDR and SDR re...

FIFO memory devices having single data rate (SDR) and dual data rat...