Jih-Nung Lee

Person

Hsinchu County, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit test method
- Patent number 10,496,505
- Issue date Dec 3, 2019
- Realtek Semiconductor Corporation
- Wen-Hsuan Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electronic apparatus and control method thereof
- Patent number 10,416,233
- Issue date Sep 17, 2019
- Realtek Semiconductor Corporation
- Chun-Yi Kuo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Debugging method executed via scan chain for scan test and related...
- Patent number 10,234,503
- Issue date Mar 19, 2019
- Realtek Semiconductor Corp.
- Chun-Yi Kuo
- G01 - MEASURING TESTING
Information Patent Grant
Method of integrated circuit scan clock domain allocation and machi...
- Patent number 9,568,553
- Issue date Feb 14, 2017
- Realtek Semiconductor Corp.
- Ming-Chung Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Estimation apparatus and method for estimating clock skew
- Patent number 9,274,543
- Issue date Mar 1, 2016
- Realtek Semiconductor Corp.
- Ying-Yen Chen
- G01 - MEASURING TESTING
Information Patent Grant
Clock edge detection device and method
- Patent number 9,160,322
- Issue date Oct 13, 2015
- Realtek Semiconductor Corporation
- Yu-Cheng Lo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
PLL status detection circuit and method thereof
- Patent number 9,157,957
- Issue date Oct 13, 2015
- Realtek Semiconductor Corporation
- Chao-Wen Tzeng
- G01 - MEASURING TESTING
Information Patent Grant
Test system which shares a register in different modes
- Patent number 8,984,354
- Issue date Mar 17, 2015
- Realtek Semiconductor Corp.
- Shuo-Fen Kuo
- G11 - INFORMATION STORAGE
Information Patent Grant
Delay difference detection and adjustment device and method
- Patent number 8,907,709
- Issue date Dec 9, 2014
- Realtek Semiconductor Corporation
- Yu-Cheng Lo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Element measurement circuit and method thereof
- Patent number 8,901,917
- Issue date Dec 2, 2014
- Realtek Semiconductor Corp.
- Ying-Yen Chen
- G01 - MEASURING TESTING
Information Patent Grant
Memory apparatus and testing method thereof
- Patent number 8,572,444
- Issue date Oct 29, 2013
- Realtek Semiconductor Corp.
- Jih-Nung Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with self-test function and method for testing the same
- Patent number 8,479,060
- Issue date Jul 2, 2013
- Realtek Semiconductor Corp.
- Shuo-Fen Kuo
- G11 - INFORMATION STORAGE
Information Patent Grant
Alternating current (AC) stress test circuit, method for evaluating...
- Patent number 8,283,941
- Issue date Oct 9, 2012
- United Microelectronics Corp.
- Sung-Nien Kuo
- G01 - MEASURING TESTING
Information Patent Grant
Microelectronic device and pin arrangement method thereof
- Patent number 7,949,919
- Issue date May 24, 2011
- Realtek Semiconductor Corp.
- Hsiang-Huang Wu
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
ELECTRONIC APPARATUS AND CONTROL METHOD THEREOF
- Publication number 20180210029
- Publication date Jul 26, 2018
- REALTEK SEMICONDUCTOR CORPORATION
- Chun-Yi KUO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT TEST METHOD
- Publication number 20180181477
- Publication date Jun 28, 2018
- REALTEK SEMICONDUCTOR CORPORATION
- WEN-HSUAN HSU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VOLTAGE AND FREQUENCY SCALING APPARATUS, SYSTEM ON CHIP AND VOLTAGE...
- Publication number 20180052506
- Publication date Feb 22, 2018
- Realtek Semiconductor Corp.
- Chun-Yi KUO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEBUGGING METHOD EXECUTED VIA SCAN CHAIN FOR SCAN TEST AND RELATED...
- Publication number 20170176522
- Publication date Jun 22, 2017
- Realtek Semiconductor Corp.
- Chun-Yi Kuo
- G01 - MEASURING TESTING
Information Patent Application
Clock edge detection device and method
- Publication number 20150022242
- Publication date Jan 22, 2015
- REALTEK SEMICONDUCTOR CORPORATION
- Yu-Cheng LO
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SCAN CLOCK GENERATOR AND RELATED METHOD THEREOF
- Publication number 20140129885
- Publication date May 8, 2014
- Realtek Semiconductor Corp.
- Ying-Yen Chen
- G01 - MEASURING TESTING
Information Patent Application
METHOD OF INTEGRATED CIRCUIT SCAN CLOCK DOMAIN ALLOCATION AND MACHI...
- Publication number 20140091812
- Publication date Apr 3, 2014
- Realtek Semiconductor Corp.
- Ming-Chung Wu
- G01 - MEASURING TESTING
Information Patent Application
ESTIMATION APPARATUS AND METHOD FOR ESTIMATING CLOCK SKEW
- Publication number 20130282318
- Publication date Oct 24, 2013
- Ying-Yen Chen
- G01 - MEASURING TESTING
Information Patent Application
Configurable Process Variation Monitoring Circuit of Die and Monito...
- Publication number 20120326701
- Publication date Dec 27, 2012
- Realtek Semiconductor Corp.
- YING-YEN CHEN
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TEST SYSTEM
- Publication number 20120304032
- Publication date Nov 29, 2012
- Shuo-Fen Kuo
- G11 - INFORMATION STORAGE
Information Patent Application
ELEMENT MEASUREMENT CIRCUIT AND METHOD THEREOF
- Publication number 20120274310
- Publication date Nov 1, 2012
- Ying-Yen CHEN
- G01 - MEASURING TESTING
Information Patent Application
Alternating Current (AC) Stress Test Circuit, Method for Evaluating...
- Publication number 20110193586
- Publication date Aug 11, 2011
- United Microelectronics Corporation
- Sung-Nien Kuo
- G01 - MEASURING TESTING
Information Patent Application
Memory with Self-Test Function and Method for Testing the Same
- Publication number 20110179323
- Publication date Jul 21, 2011
- Realtek Semiconductor Corp.
- Shuo-Fen Kuo
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY APPARATUS AND TESTING METHOD THEREOF
- Publication number 20100235695
- Publication date Sep 16, 2010
- Jih-Nung Lee
- G06 - COMPUTING CALCULATING COUNTING

Jih-Nung Lee

Person

Patents Grantslast 30 patents

Integrated circuit test method

Electronic apparatus and control method thereof

Debugging method executed via scan chain for scan test and related...

Method of integrated circuit scan clock domain allocation and machi...

Estimation apparatus and method for estimating clock skew

Clock edge detection device and method

PLL status detection circuit and method thereof

Test system which shares a register in different modes

Delay difference detection and adjustment device and method

Element measurement circuit and method thereof

Memory apparatus and testing method thereof

Memory with self-test function and method for testing the same

Alternating current (AC) stress test circuit, method for evaluating...

Microelectronic device and pin arrangement method thereof

Patents Applicationslast 30 patents

ELECTRONIC APPARATUS AND CONTROL METHOD THEREOF

INTEGRATED CIRCUIT TEST METHOD

VOLTAGE AND FREQUENCY SCALING APPARATUS, SYSTEM ON CHIP AND VOLTAGE...

DEBUGGING METHOD EXECUTED VIA SCAN CHAIN FOR SCAN TEST AND RELATED...

Clock edge detection device and method

SCAN CLOCK GENERATOR AND RELATED METHOD THEREOF

METHOD OF INTEGRATED CIRCUIT SCAN CLOCK DOMAIN ALLOCATION AND MACHI...

ESTIMATION APPARATUS AND METHOD FOR ESTIMATING CLOCK SKEW

Configurable Process Variation Monitoring Circuit of Die and Monito...

TEST SYSTEM

ELEMENT MEASUREMENT CIRCUIT AND METHOD THEREOF

Alternating Current (AC) Stress Test Circuit, Method for Evaluating...

Memory with Self-Test Function and Method for Testing the Same

MEMORY APPARATUS AND TESTING METHOD THEREOF