Jiunn Y. Wu

Person

Dou-Lio, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Multi-level conduction structure for VLSI circuits
- Patent number 5,828,121
- Issue date Oct 27, 1998
- United Microelectronics Corporation
- Water Lur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Locos technology with reduced junction leakage
- Patent number 5,668,393
- Issue date Sep 16, 1997
- United Microelectronics Corporation
- Water Lur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
LOCOS technology with reduced junction leakage
- Patent number 5,529,948
- Issue date Jun 25, 1996
- United Microelectronics Corporation
- Water Lur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Capacitor for use in DRAM cell using surface oxidized silicon nodules
- Patent number 5,512,768
- Issue date Apr 30, 1996
- United Microelectronics Corporation
- Water Lur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked capacitor process using silicon nodules
- Patent number 5,492,848
- Issue date Feb 20, 1996
- United Microelectronics Corp.
- Water Lur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming most capacitor using polysilicon islands
- Patent number 5,482,882
- Issue date Jan 9, 1996
- United Microelectronics Corporation
- Water Lur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for metal deposition without poison via
- Patent number 5,432,073
- Issue date Jul 11, 1995
- United Microelectronics Corporation
- Jiunn Y. Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-level conductor process in VLSI fabrication utilizing an air...
- Patent number 5,413,962
- Issue date May 9, 1995
- United Microelectronics Corporation
- Water Lur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Local oxidation of silicon by using aluminum spiking technology
- Patent number 5,366,925
- Issue date Nov 22, 1994
- United Microelectronics Corporation
- Water Lur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Trench isolation for both large and small areas by means of silicon...
- Patent number 5,308,786
- Issue date May 3, 1994
- United Microelectronics Corporation
- Water Lur
- H01 - BASIC ELECTRIC ELEMENTS

Jiunn Y. Wu

Person

Patents Grantslast 30 patents

Multi-level conduction structure for VLSI circuits

Locos technology with reduced junction leakage

LOCOS technology with reduced junction leakage

Capacitor for use in DRAM cell using surface oxidized silicon nodules

Stacked capacitor process using silicon nodules

Method for forming most capacitor using polysilicon islands

Method for metal deposition without poison via

Multi-level conductor process in VLSI fabrication utilizing an air...

Local oxidation of silicon by using aluminum spiking technology

Trench isolation for both large and small areas by means of silicon...