Jochen Muller

Person

Wenzenbach, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Smart card containing a carrier body for receiving at least one sys...
- Patent number 7,269,021
- Issue date Sep 11, 2007
- Infineon Techonologies AG
- Harald Gundlach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data storage configuration having a display device
- Patent number 7,140,547
- Issue date Nov 28, 2006
- Infineon Technologies AG
- Volker Frey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and device for generating digital signal patterns
- Patent number 7,117,403
- Issue date Oct 3, 2006
- Infineon Technologies AG
- Wolfgang Ernst
- G11 - INFORMATION STORAGE
Information Patent Grant
System for testing fast synchronous digital circuits, particularly...
- Patent number 7,062,690
- Issue date Jun 13, 2006
- Infineon Technologies AG
- Wolfgang Ernst
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of driving one-time operable isolation elements and circuit...
- Patent number 6,914,811
- Issue date Jul 5, 2005
- Infineon Technologies AG
- Jochen Müller
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and device for reading and for checking the time position of...
- Patent number 6,871,306
- Issue date Mar 22, 2005
- Infineon Technologies AG
- Wolfgang Ernst
- G11 - INFORMATION STORAGE
Information Patent Grant
Address counter for addressing synchronous high-frequency digital c...
- Patent number 6,862,702
- Issue date Mar 1, 2005
- Infineon Technologies AG
- Wolfgang Ernst
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and probe card configuration for testing a plurality of inte...
- Patent number 6,853,206
- Issue date Feb 8, 2005
- Infineon Technologies AG
- Michael Hübner
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit configuration for generating control signals for testing hi...
- Patent number 6,839,397
- Issue date Jan 4, 2005
- Infineon Technologies AG
- Wolfgang Ernst
- G11 - INFORMATION STORAGE
Information Patent Grant
Test configuration for the functional testing of a semiconductor chip
- Patent number 6,825,682
- Issue date Nov 30, 2004
- Infineon Technologies AG
- Dieter Kantz
- G01 - MEASURING TESTING
Information Patent Grant
Test configuration and test method for testing a plurality of integ...
- Patent number 6,762,611
- Issue date Jul 13, 2004
- Infineon Techologies AG
- Michael Hübner
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor chip, memory module and method for testing the semico...
- Patent number 6,744,127
- Issue date Jun 1, 2004
- Infineon Technologies AG
- Harry Hedler
- G11 - INFORMATION STORAGE
Information Patent Grant
System for testing fast integrated digital circuits, in particular...
- Patent number 6,721,904
- Issue date Apr 13, 2004
- Infineon Technologies AG
- Wolfgang Ernst
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated semiconductor memory device
- Patent number 6,560,149
- Issue date May 6, 2003
- Infineon Technologies AG
- Jochen Müller
- G11 - INFORMATION STORAGE
Information Patent Grant
System for testing fast synchronous semiconductor circuits
- Patent number 6,556,492
- Issue date Apr 29, 2003
- Infineon Technologies AG
- Wolfgang Ernst
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated semiconductor circuit, in particular a semiconductor mem...
- Patent number 6,545,927
- Issue date Apr 8, 2003
- Infineon Technologies AG
- Jochen Müller
- G11 - INFORMATION STORAGE
Information Patent Grant
Field-effect-controlled transistor and method for fabricating the t...
- Patent number 6,515,319
- Issue date Feb 4, 2003
- Infineon Technologies AG
- Dietrich Widmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating an integrated circuit, in particular an anti...
- Patent number 6,458,631
- Issue date Oct 1, 2002
- Infineon Technologies AG
- Axel Brintzinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Connection element in an integrated circuit having a layer structur...
- Patent number 6,429,503
- Issue date Aug 6, 2002
- Infineon Technologies AG
- Matthias Uwe Lehr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fusible link configuration in integrated circuits
- Patent number 6,407,586
- Issue date Jun 18, 2002
- Infineon Technologies AG
- Helmut Fischer
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Method and probe card configuration for testing a plurality of inte...
- Publication number 20040124863
- Publication date Jul 1, 2004
- Infineon Technologies AG
- Michael Hubner
- G01 - MEASURING TESTING
Information Patent Application
Method for driving one-time operable isolation elements and circuit...
- Publication number 20040057270
- Publication date Mar 25, 2004
- Jochen Muller
- G11 - INFORMATION STORAGE
Information Patent Application
Data storage configuration having a display device
- Publication number 20040004821
- Publication date Jan 8, 2004
- Volker Frey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Smart card containing a carrier body for receiving at least one sys...
- Publication number 20030073327
- Publication date Apr 17, 2003
- Harald Gundlach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor chip, memory module and method for testing the semico...
- Publication number 20030001236
- Publication date Jan 2, 2003
- Harry Hedler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and device for reading and for checking the time position of...
- Publication number 20020160558
- Publication date Oct 31, 2002
- Wolfgang Ernst
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD FOR FABRICATING AN INTEGRATED CIRCUIT, IN PARTICULAR AN ANTI...
- Publication number 20020155678
- Publication date Oct 24, 2002
- Axel Brintzinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated semiconductor memory device
- Publication number 20020118586
- Publication date Aug 29, 2002
- Jochen Muller
- G11 - INFORMATION STORAGE
Information Patent Application
Test configuration and test method for testing a plurality of integ...
- Publication number 20020089341
- Publication date Jul 11, 2002
- Michael Hubner
- G01 - MEASURING TESTING
Information Patent Application
System for testing fast synchronous digital circuits, particularly...
- Publication number 20020070748
- Publication date Jun 13, 2002
- Wolfgang Ernst
- G01 - MEASURING TESTING
Information Patent Application
Field-effect-controlled transistor and method for fabricating the t...
- Publication number 20020014669
- Publication date Feb 7, 2002
- Dietrich Widmann
- B82 - NANO-TECHNOLOGY
Information Patent Application
Address counter for addressing synchronous high-frequency digital c...
- Publication number 20020012286
- Publication date Jan 31, 2002
- Wolfgang Ernst
- G11 - INFORMATION STORAGE
Information Patent Application
System for testing fast synchronous semiconductor circuits
- Publication number 20020012283
- Publication date Jan 31, 2002
- Wolfgang Ernst
- G11 - INFORMATION STORAGE
Information Patent Application
System for testing fast integrated digital circuits, in particular...
- Publication number 20020010877
- Publication date Jan 24, 2002
- Wolfgang Ernst
- G11 - INFORMATION STORAGE
Information Patent Application
Method and device for generating digital signal patterns
- Publication number 20020009007
- Publication date Jan 24, 2002
- Wolfgang Ernst
- G01 - MEASURING TESTING
Information Patent Application
Circuit configuration for generating control signals for testing hi...
- Publication number 20020010878
- Publication date Jan 24, 2002
- Wolfgang Ernst
- G11 - INFORMATION STORAGE
Information Patent Application
Connection element
- Publication number 20020005586
- Publication date Jan 17, 2002
- Matthias Uwe Lehr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Test configuration for the functional testing of a semiconductor chip
- Publication number 20010043078
- Publication date Nov 22, 2001
- Dieter Kantz
- G01 - MEASURING TESTING
Information Patent Application
Integrated semiconductor circuit, in particular a semiconductor mem...
- Publication number 20010035536
- Publication date Nov 1, 2001
- Jochen Muller
- G11 - INFORMATION STORAGE
Information Patent Application
Fusible link configuration in integrated circuits
- Publication number 20010019167
- Publication date Sep 6, 2001
- Helmut Fischer
- H01 - BASIC ELECTRIC ELEMENTS

Jochen Muller

Person

Patents Grantslast 30 patents

Smart card containing a carrier body for receiving at least one sys...

Data storage configuration having a display device

Method and device for generating digital signal patterns

System for testing fast synchronous digital circuits, particularly...

Method of driving one-time operable isolation elements and circuit...

Method and device for reading and for checking the time position of...

Address counter for addressing synchronous high-frequency digital c...

Method and probe card configuration for testing a plurality of inte...

Circuit configuration for generating control signals for testing hi...

Test configuration for the functional testing of a semiconductor chip

Test configuration and test method for testing a plurality of integ...

Semiconductor chip, memory module and method for testing the semico...

System for testing fast integrated digital circuits, in particular...

Integrated semiconductor memory device

System for testing fast synchronous semiconductor circuits

Integrated semiconductor circuit, in particular a semiconductor mem...

Field-effect-controlled transistor and method for fabricating the t...

Method for fabricating an integrated circuit, in particular an anti...

Connection element in an integrated circuit having a layer structur...

Fusible link configuration in integrated circuits

Patents Applicationslast 30 patents

Method and probe card configuration for testing a plurality of inte...

Method for driving one-time operable isolation elements and circuit...

Data storage configuration having a display device

Smart card containing a carrier body for receiving at least one sys...

Semiconductor chip, memory module and method for testing the semico...

Method and device for reading and for checking the time position of...

METHOD FOR FABRICATING AN INTEGRATED CIRCUIT, IN PARTICULAR AN ANTI...

Integrated semiconductor memory device

Test configuration and test method for testing a plurality of integ...

System for testing fast synchronous digital circuits, particularly...

Field-effect-controlled transistor and method for fabricating the t...

Address counter for addressing synchronous high-frequency digital c...

System for testing fast synchronous semiconductor circuits

System for testing fast integrated digital circuits, in particular...

Method and device for generating digital signal patterns

Circuit configuration for generating control signals for testing hi...

Connection element

Test configuration for the functional testing of a semiconductor chip

Integrated semiconductor circuit, in particular a semiconductor mem...

Fusible link configuration in integrated circuits