Joe W. Zhao

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Increasing circuit speed and reducing circuit leakage by utilizing...
- Patent number 8,402,412
- Issue date Mar 19, 2013
- Xilinx, Inc.
- Cinti X. Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Identifying non-randomness in integrated circuit product yield
- Patent number 8,311,659
- Issue date Nov 13, 2012
- Xilinx, Inc.
- Cinti X. Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Estimating Icc current temperature scaling factor of an integrated...
- Patent number 8,166,445
- Issue date Apr 24, 2012
- Xilinx, Inc.
- Cinti X. Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of metal pattern inspection verification
- Patent number 8,000,519
- Issue date Aug 16, 2011
- Xilinx, Inc.
- Yongjun Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for monitoring and improving integrated circuit fabrication...
- Patent number 7,020,860
- Issue date Mar 28, 2006
- Xilinx, Inc.
- Joe W. Zhao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low dielectric constant silicon oxide-based dielectric layer for in...
- Patent number 6,756,674
- Issue date Jun 29, 2004
- LSI Logic Corporation
- Wilbur G. Catabay
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Process for forming trenches and vias in layers of low dielectric c...
- Patent number 6,368,979
- Issue date Apr 9, 2002
- LSI Logic Corporation
- Zhihai Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to obtain a low resistivity and conformity chemical vapor de...
- Patent number 6,297,555
- Issue date Oct 2, 2001
- LSI Logic Corporation
- Joe W. Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Consistent alignment mark profiles on semiconductor wafers using PV...
- Patent number 6,239,499
- Issue date May 29, 2001
- LSI Logic Corporation
- Joe W. Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process to prevent stress cracking of dielectric films on semicondu...
- Patent number 6,232,658
- Issue date May 15, 2001
- LSI Logic Corporation
- Wilbur G. Catabay
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Plasma cleaning process for openings formed in at least one low die...
- Patent number 6,204,192
- Issue date Mar 20, 2001
- LSI Logic Corporation
- Joe W. Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Consistent alignment mark profiles on semiconductor wafers using me...
- Patent number 6,157,087
- Issue date Dec 5, 2000
- LSI Logic Corporation
- Joe W. Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Consistent alignment mark profiles on semiconductor wafers using fi...
- Patent number 6,060,787
- Issue date May 9, 2000
- LSI Logic Corporation
- Joe W. Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for abrasive removal of copper from the back surface of a s...
- Patent number 6,059,637
- Issue date May 9, 2000
- LSI Logic Corporation
- Nicholas F. Pasch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for treating damaged surfaces of low dielectric constant or...
- Patent number 6,028,015
- Issue date Feb 22, 2000
- LSI Logic Corporation
- Zhihai Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal-filled via/contact opening with thin barrier layers in integr...
- Patent number 5,994,775
- Issue date Nov 30, 1999
- LSI Logic Corporation
- Joe W. Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Consistent alignment mark profiles on semiconductor wafers using fi...
- Patent number 5,981,352
- Issue date Nov 9, 1999
- LSI Logic Corporation
- Joe W. Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Consistent alignment mark profiles on semiconductor wafers using me...
- Patent number 5,966,613
- Issue date Oct 12, 1999
- LSI Corporation
- Joe W. Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for improvement of TiN CVD film quality
- Patent number 5,956,613
- Issue date Sep 21, 1999
- LSI Logic Corporation
- Joe W. Zhao
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Low stress, highly conformal CVD metal thin film
- Patent number 5,953,631
- Issue date Sep 14, 1999
- LSI Logic Corporation
- Joe W. Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Consistent alignment mark profiles on semiconductor wafers using PV...
- Patent number 5,926,720
- Issue date Jul 20, 1999
- LSI Logic Corporation
- Joe W. Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to obtain a low resistivity and conformity chemical vapor de...
- Patent number 5,895,267
- Issue date Apr 20, 1999
- LSI Logic Corporation
- Joe W. Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for eliminating peeling at end of semiconductor substrate in...
- Patent number 5,789,028
- Issue date Aug 4, 1998
- LSI Logic Corporation
- Joe W. Zhao
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method of making a barrier layer for via or contact opening of inte...
- Patent number 5,770,520
- Issue date Jun 23, 1998
- LSI Logic Corporation
- Joe W. Zhao
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Plasma clean with hydrogen gas
- Patent number 5,660,682
- Issue date Aug 26, 1997
- LSI Logic Corporation
- Joe W. Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a layer of material on a wafer
- Patent number 5,635,244
- Issue date Jun 3, 1997
- LSI Logic Corporation
- Mark I. Mayeda
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...

Joe W. Zhao

Person

Patents Grantslast 30 patents

Increasing circuit speed and reducing circuit leakage by utilizing...

Identifying non-randomness in integrated circuit product yield

Estimating Icc current temperature scaling factor of an integrated...

Method of metal pattern inspection verification

Method for monitoring and improving integrated circuit fabrication...

Low dielectric constant silicon oxide-based dielectric layer for in...

Process for forming trenches and vias in layers of low dielectric c...

Method to obtain a low resistivity and conformity chemical vapor de...

Consistent alignment mark profiles on semiconductor wafers using PV...

Process to prevent stress cracking of dielectric films on semicondu...

Plasma cleaning process for openings formed in at least one low die...

Consistent alignment mark profiles on semiconductor wafers using me...

Consistent alignment mark profiles on semiconductor wafers using fi...

Process for abrasive removal of copper from the back surface of a s...

Process for treating damaged surfaces of low dielectric constant or...

Metal-filled via/contact opening with thin barrier layers in integr...

Consistent alignment mark profiles on semiconductor wafers using fi...

Consistent alignment mark profiles on semiconductor wafers using me...

Method for improvement of TiN CVD film quality

Low stress, highly conformal CVD metal thin film

Consistent alignment mark profiles on semiconductor wafers using PV...

Method to obtain a low resistivity and conformity chemical vapor de...

Method for eliminating peeling at end of semiconductor substrate in...

Method of making a barrier layer for via or contact opening of inte...

Plasma clean with hydrogen gas

Method of forming a layer of material on a wafer