Johannes Stecker

Person

Munich, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Multi-port DRAM architecture for accessing different memory partitions
- Patent number 8,914,589
- Issue date Dec 16, 2014
- Infineon Technologies AG
- Peter Gregorius
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system including plural memory controllers and a memory...
- Patent number 8,495,310
- Issue date Jul 23, 2013
- Qimonda AG
- Peter Gregorius
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Memory system with extended memory density capability
- Patent number 8,271,827
- Issue date Sep 18, 2012
- Qimonda
- Christoph Bilger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed command and address bus architecture for a memory modul...
- Patent number 8,161,219
- Issue date Apr 17, 2012
- Qimonda AG
- Michael Bruennert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for determining a skew
- Patent number 8,144,755
- Issue date Mar 27, 2012
- Michael Bruennert
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multi-die memory, apparatus and multi-die memory stack
- Patent number 8,120,958
- Issue date Feb 21, 2012
- Qimonda AG
- Christoph Bilger
- G11 - INFORMATION STORAGE
Information Patent Grant
Bus termination system and method
- Patent number 8,041,865
- Issue date Oct 18, 2011
- Qimonda AG
- Michael Bruennert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory circuit
- Patent number 8,015,438
- Issue date Sep 6, 2011
- Qimonda AG
- Michael Bruennert
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit with wireless connection
- Patent number 7,928,525
- Issue date Apr 19, 2011
- Qimonda AG
- Christoph Bilger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for storage device with a logic unit and metho...
- Patent number 7,920,433
- Issue date Apr 5, 2011
- Qimonda AG
- Christoph Bilger
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed memory architecture
- Patent number 7,848,153
- Issue date Dec 7, 2010
- Qimonda AG
- Michael Bruennert
- G11 - INFORMATION STORAGE
Information Patent Grant
Command protocol for integrated circuits
- Patent number 7,844,798
- Issue date Nov 30, 2010
- Qimonda AG
- Andreas Gärtner
- G11 - INFORMATION STORAGE
Information Patent Grant
Horizontal dual in-line memory modules
- Patent number 7,771,206
- Issue date Aug 10, 2010
- Qimonda AG
- Michael Bruennert
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Semiconductor memory arrangement with branched control and address bus
- Patent number 7,411,843
- Issue date Aug 12, 2008
- Infineon Technologies AG
- Hermann Ruckerbauer
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory array with serial control/address bus
- Patent number 7,397,684
- Issue date Jul 8, 2008
- Infineon Technologies, AG
- Hermann Ruckerbauer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Temperature independent oscillator
- Patent number 5,870,345
- Issue date Feb 9, 1999
- Siemens Aktiengesellschaft
- Johannes Stecker
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated buffer circuit which functions independently of fluctuat...
- Patent number 5,774,014
- Issue date Jun 30, 1998
- Siemens Aktiengesellschaft
- Johannes Stecker
- G05 - CONTROLLING REGULATING
Information Patent Grant
Semiconductor component with protective structure for protecting ag...
- Patent number 5,646,434
- Issue date Jul 8, 1997
- Siemens Aktiengesellschaft
- Ioannis Chrysostomides
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Stacking Technique for Circuit Devices
- Publication number 20110034045
- Publication date Feb 10, 2011
- QIMONDA AG
- Christoph Bilger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Distributed Command and Address Bus Architecture
- Publication number 20100082871
- Publication date Apr 1, 2010
- Michael Bruennert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-PORT DRAM ARCHITECTURE
- Publication number 20100077139
- Publication date Mar 25, 2010
- PETER GREGORIUS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI MASTER DRAM ARCHITECTURE
- Publication number 20100077157
- Publication date Mar 25, 2010
- PETER GREGORIUS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Horizontal Dual In-line Memory Modules
- Publication number 20100062621
- Publication date Mar 11, 2010
- MICHAEL BRUENNERT
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
High Speed Memory Architecture
- Publication number 20100046266
- Publication date Feb 25, 2010
- Michael Bruennert
- G11 - INFORMATION STORAGE
Information Patent Application
Stacked Memory Module
- Publication number 20100032820
- Publication date Feb 11, 2010
- Michael Bruennert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Bus Termination System and Method
- Publication number 20100030934
- Publication date Feb 4, 2010
- Michael Bruennert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR CONTROLLING A MEMORY MODULE AND MEMORY CONTROL UNIT
- Publication number 20090287957
- Publication date Nov 19, 2009
- Christoph Bilger
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated Circuit with Improved Data Rate
- Publication number 20090267678
- Publication date Oct 29, 2009
- QIMONDA AG
- Christoph Bilger
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Integrated circuit with wireless connection
- Publication number 20090267084
- Publication date Oct 29, 2009
- QIMONDA AG
- Christoph Bilger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DRAM with Page Access
- Publication number 20090190432
- Publication date Jul 30, 2009
- Christoph BILGER
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR STORAGE DEVICE WITH A LOGIC UNIT AND METHO...
- Publication number 20090175100
- Publication date Jul 9, 2009
- Christoph Bilger
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE, METHOD FOR ACCESSING A MEMORY DEVICE AND METHOD FOR...
- Publication number 20090175115
- Publication date Jul 9, 2009
- Christoph Bilger
- G11 - INFORMATION STORAGE
Information Patent Application
Multi-die Memory, Apparatus and Multi-die Memory Stack
- Publication number 20090161401
- Publication date Jun 25, 2009
- Christoph Bilger
- G11 - INFORMATION STORAGE
Information Patent Application
Command Protocol for Integrated Circuits
- Publication number 20090158010
- Publication date Jun 18, 2009
- QIMONDA AG
- Andreas Gartner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory System With Extended Memory Density Capability
- Publication number 20090150710
- Publication date Jun 11, 2009
- Christoph Bilger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Circuit
- Publication number 20090144583
- Publication date Jun 4, 2009
- Qimonda AG
- Michael Bruennert
- G11 - INFORMATION STORAGE
Information Patent Application
Method and Apparatus for Determining a Skew
- Publication number 20090141843
- Publication date Jun 4, 2009
- Qimonda AG
- Michael Bruennert
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD AND APPARATUS FOR MONITORING A MEMORY DEVICE
- Publication number 20090129189
- Publication date May 21, 2009
- Christoph Bilger
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor memory array with serial control/address bus
- Publication number 20070058408
- Publication date Mar 15, 2007
- Hermann Ruckerbauer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor memory arrangement with branched control and address bus
- Publication number 20070058409
- Publication date Mar 15, 2007
- Hermann Ruckerbauer
- G11 - INFORMATION STORAGE

Johannes Stecker

Person

Patents Grantslast 30 patents

Multi-port DRAM architecture for accessing different memory partitions

Method and system including plural memory controllers and a memory...

Memory system with extended memory density capability

Distributed command and address bus architecture for a memory modul...

Method and apparatus for determining a skew

Multi-die memory, apparatus and multi-die memory stack

Bus termination system and method

Memory circuit

Integrated circuit with wireless connection

Method and apparatus for storage device with a logic unit and metho...

High speed memory architecture

Command protocol for integrated circuits

Horizontal dual in-line memory modules

Semiconductor memory arrangement with branched control and address bus

Semiconductor memory array with serial control/address bus

Temperature independent oscillator

Integrated buffer circuit which functions independently of fluctuat...

Semiconductor component with protective structure for protecting ag...

Patents Applicationslast 30 patents

Stacking Technique for Circuit Devices

Distributed Command and Address Bus Architecture

MULTI-PORT DRAM ARCHITECTURE

MULTI MASTER DRAM ARCHITECTURE

Horizontal Dual In-line Memory Modules

High Speed Memory Architecture

Stacked Memory Module

Bus Termination System and Method

METHOD FOR CONTROLLING A MEMORY MODULE AND MEMORY CONTROL UNIT

Integrated Circuit with Improved Data Rate

Integrated circuit with wireless connection

DRAM with Page Access

METHOD AND APPARATUS FOR STORAGE DEVICE WITH A LOGIC UNIT AND METHO...

MEMORY DEVICE, METHOD FOR ACCESSING A MEMORY DEVICE AND METHOD FOR...

Multi-die Memory, Apparatus and Multi-die Memory Stack

Command Protocol for Integrated Circuits

Memory System With Extended Memory Density Capability

Memory Circuit

Method and Apparatus for Determining a Skew

METHOD AND APPARATUS FOR MONITORING A MEMORY DEVICE

Semiconductor memory array with serial control/address bus

Semiconductor memory arrangement with branched control and address bus