Patent Application
20100032820
This invention relates generally to electronic systems and methods, and, in particular embodiments, to a stacked ultra high performance memory module.
Memory devices are used in many applications, such as computers, calculators, and cellular phones, as examples. Packaging of memory devices varies in different applications. For many years, single in-line memory modules (SIMMs) were used in computers. However, beginning with memory used for more recent 64-bit processors, dual in-line memory modules (DIMMs) have become more common. DIMMs have separate electrical contacts on each side of the module, while the contacts on SIMMs on both sides are redundant.
Another known connection for a memory module 102 to a motherboard 114 is shown in a cross-sectional view in
The memory slot connectors 116 and 118 provide added flexibility because each system can include one or more slots that can be populated and upgraded as needed. However, this flexibility comes at a cost. Memory slot connectors 116 and 118 can cause signal integrity problems, due to the parasitic impedance of the connections.
Alternatively, memory chips 104 can be directly mounted on the motherboard. This solution can provide better signal integrity than memory slot connectors 116 or 118 but is inflexible since the memory is not easily replaceable. Many computer users are not capable of desoldering and soldering memory chips to upgrade computers.
The CPU 122 is coupled to the motherboard 114 using the CPU socket 124. The CPU socket 124 provides a high performance connection for the CPU 122 to the motherboard 114, e.g., having a higher performance than the memory slot connectors 116. The memory slot connectors 116 slow down and limit the speed of the motherboard 114 of the computing system.
Embodiments of the present invention provide technical advantages by providing novel memory modules and computing systems, and methods of manufacture thereof. The memory modules comprise stacked ultra high performance memory modules that overcome the signal integrity limitations of state-of-the-art interconnect techniques for memory modules.
In accordance with one embodiment of the present invention, a memory module includes a substrate having a first side and a second side opposed to the first side. A plurality of pins is disposed on the first side of the substrate. A first plurality of memory chips is arranged in a first chip layer, the first chip layer overlying the second side of the substrate. Electrical contacts of the first plurality of memory chips are electrically coupled to the pins. A second plurality of memory chips is arranged in a second chip layer, the second chip layer overlying the first chip layer. Electrical contacts of the second plurality of memory chips are electrically coupled to the pins.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments of the present invention and are not necessarily drawn to scale.
The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
Embodiments of the present invention achieve technical advantages by using a socket similar to or the same as a socket for a CPU, advantageously providing a state-of the art high performance interconnect for a memory module, resulting in an optimization of the signal quality for the memory module and increasing the speed.
In one aspect, a module stacking technique is combined with state-of-the-art package and mounting techniques to allow a highly flexible, high performance, high density memory module. Embodiments can overcome the signal integrity limitations of state-of-the-art interconnect techniques for memory modules. As an example, memory modules can use existing high performance interconnect techniques such as those used for CPU (main board) socket. This technique can provide flexibility in memory density by allowing for the addition or replacement of memory modules.
In various embodiments, memory sockets can include a huge pin count, which can be utilized for optimal signal and power routing. This can be useful for memory modules that use high density stacking techniques. These sockets also tend to have a well defined foot print. Electrical routing between the CPU and the memory socket can also be accomplished easily.
The present invention will be described with respect to preferred embodiments in a specific context, namely as memory modules used in computing systems. The invention may also be applied, however, to other applications that require memory modules, for example.
The computing system 260 includes a circuit board 214, commonly referred to as a motherboard. The processor socket 124 and the memory socket 234 are mounted on the circuit board 214. In a preferred embodiment, the memory module 232 is a stacked ultra high performance memory module, as will be discussed in more detail below. In an embodiment, the memory module 232 is connected to the memory socket 234 in the same manner that the processor 222 is connected to the processor socket 124. The memory module 232 is functionally coupled to the processor 222 via the circuit board 214, e.g., by metal or conductive lines and wiring formed in or on the circuit board 214. As shown in the figure, the memory 232 can be functionally coupled to the processor via a memory controller 228, which can either be integrated in the processor 222 or as a separate chip, which is shown in phantom. Other components on the motherboard are not shown.
A block diagram of the computing system 260 is shown in
The bus 262 is coupled to a number of components and communicates with the microprocessor 222 via the controller 228. Four examples of components that can be coupled to the bus 262 are shown, i.e., user input/output 254 (which could include a display, mouse, keyboard, microphone or other), network interface card 256, hard disk drive 258 and DVD drive 259. These examples are provided only to show the types of devices that can be utilized in a computer system 260. Other busses or components could be used.
The processor 222 may comprise a microprocessor and may comprise the CPU of the computing system 260, for example. The memory module 232 may comprise a DRAM memory module or other types of memory. For example, the memory module 232 can be a non-volatile memory or a static memory.
The memory socket 234 is formed from an insulating material such as plastic or other dielectric material, with a number of openings 238 in the insulating material and electrical connections (not visible in the figure) within the openings. The openings 238 and connections are adapted to receive and retain pins 236 on the memory module 232. In this example, the pins are arranged in rows around the perimeter of the memory module 232. Each module pin 236 is electrically connected to the system via an associated opening 238 in the socket 234. The memory socket 234 comprises a high reliability, high performance connection device having high conductivity of the hardware of individual sockets within the openings 238.
The socket 234 may comprise a substantially rectangular or square shape that conforms to the footprint of the memory module, for example. In one example, the socket has dimensions of about 15 mm by 15 mm. As such, two sockets would not require much more surface area than two corresponding memory slots in a conventional system. The memory would, however, have a much lower profile since the module is mounted by the bottom side rather than an edge. Much of this space is saved by encapsulating bare die in the module.
In another example, a 30 mm×30 mm socket could have as many as eight 1 G DDR2 DRAM's per layer based on a chip size (silicon) of 12 mm×7 mm, which is an average size for this type of DRAM. In order to be compatible with an average DIMM when comparing the number of attached DRAM's there would be a need for a minimum of two layers since the average number of DRAM's per DIMM is typically between 16 and 32. Of course, one could also go down to a 15 mm×15 mm socket size for a four DRAM per layer module with four layers. In general, a module could include any number of DRAMs per layer.
The interface between the memory module 232 and the memory socket 234 may be based on a pin grid array (PGA) architecture. For example, short, stiff pins 236 on the underside of the module 232 mate with the holes or openings 238 in the socket 234. The hardware in the openings 238 may comprise zero insertion force (ZIF) sockets that allow the pins 236 to be inserted with little resistance, and then a lever (not shown) on the socket 234 is flipped, causing the pins 236 to be gripped firmly and provide a reliable contact. Alternatively, other types of sockets may be used for the socket 234.
The memory socket 234 may comprise the same type of connections, e.g., may comprise the same type of hardware inside the openings 238 as the hardware inside the openings of the processor socket (labeled 124 in
The number of openings 238 of the memory socket 234 may be the same as or greater than the number of pins 236 on the memory module 232. As an example, a module socket may include one hundred or more pins, e.g., over two hundred in some embodiments. For example, a known 240-pin DIMM can be used for DDR2 SDRAM, DDR3 SDRAM and FB-DIMM DRAM. The module of the present invention can include at least this number of contacts and potentially more. For example, a Socket 7 compliant socket, which can be used with various microprocessors, has 321 contacts. Additional contacts could allow for more functionality, as well as more power/ground connections, in the memory. In embodiments wherein the number of openings 238 of the memory socket 234 is greater than the number of connections needed by the module 232, some of the pins 236 of the memory module 232 may comprise dummy pins (e.g., grounded pins) or some of the openings will not have a corresponding pin inserted therein or the openings which are not needed for a single memory module, as shown in
The memory module 232 includes a substrate 250a. The pins 236 are disposed on the bottom side of the substrate 250a. In the illustrated embodiment, the pins 236 may be arranged in rows around a periphery of the bottom side of the substrate 250a. The pins can be in other configurations as well, e.g., in an array over the entire bottom surface.
Memory chips 204a are arranged in a first chip layer 240a that overlies the top side of the substrate 250a. The chips 204 can attached to the substrate 250a using an adhesive, as an example. Electrical contacts of the memory chips 204a are electrically coupled to the pins 236, e.g., by wire bonds and metal lines (not shown) on the substrate 250a. Alternatively, the memory chips 204a can include through silicon vias for electrically coupling to the substrate 250a. As another example, the memory chips 204 can be formed with a redistribution layer and include contacts, e.g., compliant bumps, so that the chip is mounted face down and connected to the substrate via the bumps.
A second group of memory chips 204b is arranged in a second chip layer 240b that overlies the first chip layer 240a. Electrical contacts of the second group of memory chips 204b are also electrically coupled to the pins 236. The second plurality of memory chips 204b can be mounted on a substrate 250b and electrically coupled to the substrate 250b using wire bonds or through silicon/substrate vias (as described below). The substrate 250b may include bond pads on a back surface thereof that are coupled to bond pads on the first plurality of memory chips 204a of the first chip layer 240a. In other words, the substrate 250b may be an intermediate substrate disposed between the first chip layer 240a and the memory chips 204b of the second chip layer 240b.
Alternatively, the electrical contacts of the second plurality of memory chips 204b may be electrically coupled to the electrical contacts of the first plurality of memory chips 204a, which are electrically coupled to the pins 236. In this example, the memory chips 204 may use through silicon vias, e.g., an electrical connector that extends through the substrate of the chip. As another alternative, the second layer of chips can be connected via compliant bumps as described above.
The memory chips 204 are preferably DRAM chips, although alternatively, other types of memory devices could also utilize concepts of the present invention. The DRAM chips may comprise synchronous DRAM chips, each DRAM chip including at least 256 million memory cells, as one example. For example, 1 Gbit or 2 Gbit DDR SDRAM chips can be included in the memory module 232. In the illustrated example, a 64-bit data bus can be achieved by including eight x8 chips arranged in two layers in one embodiment. In another embodiment, more than one rank can be included in a module so that some of the data pins for different memory chips are connected in parallel. This embodiment can be especially useful in embodiments with more than two layers or more than four chips per layer.
Electrical contacts of the first plurality of memory chips 204a of the first chip layer 240a may be electrically connected to electrical contacts of the substrate 250a via first wire bonds (not shown in
The through vias 248 provide electrical connections between the chip layers 240. For example, the through vias 248 of the substrates 250a, 250b, 250c, and 250d may be connected together using solder bonds or a conductive adhesive. For example, the data bus, as well as some of the address and control lines, can be coupled to multiple chips. Other control lines such as clock enable (CKE), chip select (CS), on die termination control (ODT) and, possibly a portion of the address bus, could be connected individually to only some of the chips. In one embodiment, each layer 240 of the module can form one rank of memory.
Only three chip layers 240 are shown in
While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.
