John B. DeForge

Person

Barre, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Microchip level shared array repair
- Patent number 11,462,295
- Issue date Oct 4, 2022
- International Business Machines Corporation
- Timothy Meehan
- G11 - INFORMATION STORAGE
Information Patent Grant
Performance-screen ring oscillator with switchable features
- Patent number 11,146,251
- Issue date Oct 12, 2021
- International Business Machines Corporation
- John B. DeForge
- G01 - MEASURING TESTING
Information Patent Grant
Method and structures for personalizing lithography
- Patent number 11,067,895
- Issue date Jul 20, 2021
- International Business Machines Corporation
- John B. Deforge
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Optimizing error correcting code in three-dimensional stacked memory
- Patent number 10,740,177
- Issue date Aug 11, 2020
- International Business Machines Corporation
- Saravanan Sethuraman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Three-dimensional stacked memory optimizations for latency and power
- Patent number 10,534,545
- Issue date Jan 14, 2020
- International Business Machines Corporation
- Diyanesh B. Chinnakkonda Vidyapoornachary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Three-dimensional stacked memory access optimization
- Patent number 10,528,288
- Issue date Jan 7, 2020
- International Business Machines Corporation
- Diyanesh B. Chinnakkonda Vidyapoornachary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Independently driving built-in self test circuitry over a range of...
- Patent number 10,254,340
- Issue date Apr 9, 2019
- International Business Machines Corporation
- John B. DeForge
- G01 - MEASURING TESTING
Information Patent Grant
Lateral non-volatile storage cell
- Patent number 10,153,291
- Issue date Dec 11, 2018
- International Business Machines Corporation
- John B. DeForge
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lateral non-volatile storage cell
- Patent number 10,109,639
- Issue date Oct 23, 2018
- International Business Machines Corporation
- John B. DeForge
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
On chip electrostatic discharge (ESD) event monitoring
- Patent number 9,673,116
- Issue date Jun 6, 2017
- International Business Machines Corporation
- John B. DeForge
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stress balancing of circuits
- Patent number 9,472,269
- Issue date Oct 18, 2016
- GLOBALFOUNDRIES Inc.
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Grant
Light activated test connections
- Patent number 9,437,670
- Issue date Sep 6, 2016
- GLOBALFOUNDRIES Inc.
- Nathaniel R. Chadwick
- G01 - MEASURING TESTING
Information Patent Grant
Creating deep trenches on underlying substrate
- Patent number 8,860,113
- Issue date Oct 14, 2014
- International Business Machines Corporation
- Jennifer E. Appleyard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Creating deep trenches on underlying substrate
- Patent number 8,586,444
- Issue date Nov 19, 2013
- International Business Machines Corporation
- Jennifer E. Appleyard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrical mask identification of memory modules
- Patent number 6,570,254
- Issue date May 27, 2003
- International Business Machines Corporation
- John B. DeForge
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Electrical mask identification of memory modules
- Patent number 6,268,228
- Issue date Jul 31, 2001
- International Business Machines Corporation
- John B. DeForge
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY

Patents Applicationslast 30 patents

Information Patent Application
MICROCHIP LEVEL SHARED ARRAY REPAIR
- Publication number 20210319845
- Publication date Oct 14, 2021
- International Business Machines Corporation
- Timothy MEEHAN
- G11 - INFORMATION STORAGE
Information Patent Application
PERFORMANCE-SCREEN RING OSCILLATOR WITH SWITCHABLE FEATURES
- Publication number 20210281248
- Publication date Sep 9, 2021
- International Business Machines Corporation
- John B. DeForge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZING ERROR CORRECTING CODE IN THREE-DIMENSIONAL STACKED MEMORY
- Publication number 20190220351
- Publication date Jul 18, 2019
- International Business Machines Corporation
- SARAVANAN SETHURAMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREE-DIMENSIONAL STACKED MEMORY OPTIMIZATIONS FOR LATENCY AND POWER
- Publication number 20190187915
- Publication date Jun 20, 2019
- International Business Machines Corporation
- Diyanesh B. Chinnakkonda Vidyapoornachary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREE-DIMENSIONAL STACKED MEMORY ACCESS OPTIMIZATION
- Publication number 20190187930
- Publication date Jun 20, 2019
- International Business Machines Corporation
- Diyanesh B. Chinnakkonda Vidyapoornachary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LATERAL NON-VOLATILE STORAGE CELL
- Publication number 20180358366
- Publication date Dec 13, 2018
- International Business Machines Corporation
- John B. DeForge
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND STRUCTURES FOR PERSONALIZING LITHOGRAPHY
- Publication number 20180203341
- Publication date Jul 19, 2018
- International Business Machines Corporation
- John B. Deforge
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ROBUST BUILT-IN SELF TEST CIRCUITRY
- Publication number 20180080986
- Publication date Mar 22, 2018
- International Business Machines Corporation
- John B. DeForge
- G01 - MEASURING TESTING
Information Patent Application
STRESS BALANCING OF CIRCUITS
- Publication number 20150228357
- Publication date Aug 13, 2015
- International Business Machines Corporation
- Igor ARSOVSKI
- G11 - INFORMATION STORAGE
Information Patent Application
ON CHIP ELECTROSTATIC DISCHARGE (ESD) EVENT MONITORING
- Publication number 20140191778
- Publication date Jul 10, 2014
- International Business Machines Corporation
- John B. DeForge
- G01 - MEASURING TESTING
Information Patent Application
LIGHT ACTIVATED TEST CONNECTIONS
- Publication number 20140145747
- Publication date May 29, 2014
- International Business Machines Corporation
- Nathaniel R. CHADWICK
- G01 - MEASURING TESTING
Information Patent Application
CREATING DEEP TRENCHES ON UNDERLYING SUBSTRATE
- Publication number 20140021585
- Publication date Jan 23, 2014
- International Business Machines Corporation
- Jennifer E. Appleyard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CREATING DEEP TRENCHES ON UNDERLYING SUBSTRATE
- Publication number 20130249052
- Publication date Sep 26, 2013
- International Business Machines Corporation
- Jennifer E. Appleyard
- H01 - BASIC ELECTRIC ELEMENTS

John B. DeForge

Person

Patents Grantslast 30 patents

Microchip level shared array repair

Performance-screen ring oscillator with switchable features

Method and structures for personalizing lithography

Optimizing error correcting code in three-dimensional stacked memory

Three-dimensional stacked memory optimizations for latency and power

Three-dimensional stacked memory access optimization

Independently driving built-in self test circuitry over a range of...

Lateral non-volatile storage cell

Lateral non-volatile storage cell

On chip electrostatic discharge (ESD) event monitoring

Stress balancing of circuits

Light activated test connections

Creating deep trenches on underlying substrate

Creating deep trenches on underlying substrate

Electrical mask identification of memory modules

Electrical mask identification of memory modules

Patents Applicationslast 30 patents

MICROCHIP LEVEL SHARED ARRAY REPAIR

PERFORMANCE-SCREEN RING OSCILLATOR WITH SWITCHABLE FEATURES

OPTIMIZING ERROR CORRECTING CODE IN THREE-DIMENSIONAL STACKED MEMORY

THREE-DIMENSIONAL STACKED MEMORY OPTIMIZATIONS FOR LATENCY AND POWER

THREE-DIMENSIONAL STACKED MEMORY ACCESS OPTIMIZATION

LATERAL NON-VOLATILE STORAGE CELL

METHOD AND STRUCTURES FOR PERSONALIZING LITHOGRAPHY

ROBUST BUILT-IN SELF TEST CIRCUITRY

STRESS BALANCING OF CIRCUITS

ON CHIP ELECTROSTATIC DISCHARGE (ESD) EVENT MONITORING

LIGHT ACTIVATED TEST CONNECTIONS

CREATING DEEP TRENCHES ON UNDERLYING SUBSTRATE

CREATING DEEP TRENCHES ON UNDERLYING SUBSTRATE