John D. Heightley

Person

Monument, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Configurable architecture hybrid analog/digital delay locked loop (...
- Patent number 7,876,137
- Issue date Jan 25, 2011
- ProMOS Technologies Pte. Ltd.
- John D. Heightley
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit and technique for adjusting and accurately controlling cloc...
- Patent number 7,518,425
- Issue date Apr 14, 2009
- ProMOS Technologies Pte. Ltd.
- John D. Heightley
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Use of multiple voltage controlled delay lines for precise alignmen...
- Patent number 7,474,136
- Issue date Jan 6, 2009
- ProMOS Technologies Pte. Ltd.
- John D. Heightley
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual equalization devices for long data line pairs
- Patent number 7,218,564
- Issue date May 15, 2007
- ProMos Technologies Inc.
- Jon Allan Faue
- G11 - INFORMATION STORAGE
Information Patent Grant
Low voltage differential amplifier circuit for wide voltage range o...
- Patent number 7,167,052
- Issue date Jan 23, 2007
- ProMos Technologies Inc.
- John D. Heightley
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low voltage differential amplifier circuit and a sampled low power...
- Patent number 7,102,439
- Issue date Sep 5, 2006
- ProMos Technologies Inc.
- John D. Heightley
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Voltage-controlled analog delay locked loop
- Patent number 7,071,745
- Issue date Jul 4, 2006
- ProMos Technologies, Inc.
- John D. Heightley
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low voltage differential amplifier circuit and bias control techniq...
- Patent number 7,061,322
- Issue date Jun 13, 2006
- ProMos Technologies Inc.
- John Heightley
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multi-bank memory array architecture utilizing topologically non-un...
- Patent number 6,741,488
- Issue date May 25, 2004
- ProMos Technologies Inc.
- John Heightley
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for eliminating pulse width variations in digital...
- Patent number 6,469,559
- Issue date Oct 22, 2002
- Mosel Vitelic, Inc.
- John Heightley
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic data amplifier with built-in voltage level shifting
- Patent number 6,445,621
- Issue date Sep 3, 2002
- Mosel Vitelic, Inc.
- John D. Heightley
- G11 - INFORMATION STORAGE
Information Patent Grant
Two-phase charge-sharing data latch for memory circuit
- Patent number 6,434,069
- Issue date Aug 13, 2002
- United Memories, Inc.
- John D. Heightley
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for supporting sequential burst counts in double...
- Patent number 6,415,374
- Issue date Jul 2, 2002
- Mosel Vitelic, Inc.
- Jon Allan Faue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method of compensating for non-linear voltage-to-delay c...
- Patent number 6,359,487
- Issue date Mar 19, 2002
- Mosel Vitelic Inc
- John Heightley
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for eliminating pulse width variations in digital...
- Patent number 6,339,354
- Issue date Jan 15, 2002
- Mosel Vitelic, Inc.
- John Heightley
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Architecture for high speed memory circuit having a relatively larg...
- Patent number 6,339,541
- Issue date Jan 15, 2002
- United Memories, Inc.
- Kim Carver Hardee
- G11 - INFORMATION STORAGE
Information Patent Grant
Asynchronously equillibrated and pre-charged static ram
- Patent number 4,355,377
- Issue date Oct 19, 1982
- INMOS Corporation
- Rahul Sud
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
CONFIGURABLE ARCHITECTURE HYBRID ANALOG/DIGITAL DELAY LOCKED LOOP (...
- Publication number 20100123494
- Publication date May 20, 2010
- PROMOS TECHNOLOGIES PTE.LTD.
- John D. Heightley
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
USE OF MULTIPLE VOLTAGE CONTROLLED DELAY LINES FOR PRECISE ALIGNMEN...
- Publication number 20080278211
- Publication date Nov 13, 2008
- PROMOS TECHNOLOGIES PTE.LTD.
- John D. Heightley
- G11 - INFORMATION STORAGE
Information Patent Application
CIRCUIT AND TECHNIQUE FOR ADJUSTING AND ACCURATELY CONTROLLING CLOC...
- Publication number 20080186068
- Publication date Aug 7, 2008
- PROMOS TECHNOLOGIES PTE.LTD.
- John D. Heightley
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
System and method for controlling the drive strength of output driv...
- Publication number 20070103124
- Publication date May 10, 2007
- United Memories, Inc.
- John D. Heightley
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method for improving the timing resolution of DLL controlled delay...
- Publication number 20070096787
- Publication date May 3, 2007
- United Memories, Inc.
- John D. Heightley
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Dual equalization devices for long data line pairs
- Publication number 20060023529
- Publication date Feb 2, 2006
- Jon Allan Faue
- G11 - INFORMATION STORAGE
Information Patent Application
Low voltage differential amplifier circuit for wide voltage range o...
- Publication number 20050275461
- Publication date Dec 15, 2005
- John D. Heightley
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW VOLTAGE DIFFERENTIAL AMPLIFIER CIRCUIT AND A SAMPLED LOW POWER...
- Publication number 20050275462
- Publication date Dec 15, 2005
- John D. Heightley
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Low voltage differential amplifier circuit and bias control techniq...
- Publication number 20050275463
- Publication date Dec 15, 2005
- John Heightley
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Voltage-controlled analog delay locked loop
- Publication number 20050174155
- Publication date Aug 11, 2005
- John D. Heightley
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MULTI-BANK MEMORY ARRAY ARCHITECTURE UTILIZING TOPOLOGICALLY NON-UN...
- Publication number 20040095796
- Publication date May 20, 2004
- John Heightley
- G11 - INFORMATION STORAGE
Information Patent Application
System and method for eliminating pulse width variations in digital...
- Publication number 20020053932
- Publication date May 9, 2002
- John Heightley
- H03 - BASIC ELECTRONIC CIRCUITRY

John D. Heightley

Person

Patents Grantslast 30 patents

Configurable architecture hybrid analog/digital delay locked loop (...

Circuit and technique for adjusting and accurately controlling cloc...

Use of multiple voltage controlled delay lines for precise alignmen...

Dual equalization devices for long data line pairs

Low voltage differential amplifier circuit for wide voltage range o...

Low voltage differential amplifier circuit and a sampled low power...

Voltage-controlled analog delay locked loop

Low voltage differential amplifier circuit and bias control techniq...

Multi-bank memory array architecture utilizing topologically non-un...

System and method for eliminating pulse width variations in digital...

Dynamic data amplifier with built-in voltage level shifting

Two-phase charge-sharing data latch for memory circuit

System and method for supporting sequential burst counts in double...

System and method of compensating for non-linear voltage-to-delay c...

System and method for eliminating pulse width variations in digital...

Architecture for high speed memory circuit having a relatively larg...

Asynchronously equillibrated and pre-charged static ram

Patents Applicationslast 30 patents

CONFIGURABLE ARCHITECTURE HYBRID ANALOG/DIGITAL DELAY LOCKED LOOP (...

USE OF MULTIPLE VOLTAGE CONTROLLED DELAY LINES FOR PRECISE ALIGNMEN...

CIRCUIT AND TECHNIQUE FOR ADJUSTING AND ACCURATELY CONTROLLING CLOC...

System and method for controlling the drive strength of output driv...

Method for improving the timing resolution of DLL controlled delay...

Dual equalization devices for long data line pairs

Low voltage differential amplifier circuit for wide voltage range o...

LOW VOLTAGE DIFFERENTIAL AMPLIFIER CIRCUIT AND A SAMPLED LOW POWER...

Low voltage differential amplifier circuit and bias control techniq...

Voltage-controlled analog delay locked loop

MULTI-BANK MEMORY ARRAY ARCHITECTURE UTILIZING TOPOLOGICALLY NON-UN...

System and method for eliminating pulse width variations in digital...