John E. Gersbach

Person

Burlington, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
CVF current reference with standby mode
- Patent number 6,198,339
- Issue date Mar 6, 2001
- International Business Machines Corporation
- John E. Gersbach
- G05 - CONTROLLING REGULATING
Information Patent Grant
Slew rate control circuit
- Patent number 6,118,261
- Issue date Sep 12, 2000
- International Business Machines Corp.
- Charles Karoly Erdelyi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power voltage translation circuit
- Patent number 6,097,215
- Issue date Aug 1, 2000
- International Business Machines Corporation
- John S. Bialas
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Pull-up and pull-down circuits
- Patent number 6,031,403
- Issue date Feb 29, 2000
- International Business Machines Corporation
- John Edwin Gersbach
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
On-chip thermometry for control of chip operating temperature
- Patent number 5,873,053
- Issue date Feb 16, 1999
- International Business Machines Corporation
- Wilbur D. Pricer
- G01 - MEASURING TESTING
Information Patent Grant
Self-timed circuit having critical path timing detection
- Patent number 5,870,404
- Issue date Feb 9, 1999
- International Business Machines Corporation
- Frank D. Ferraiolo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Variable-speed phase-locked loop system with on-the-fly switching a...
- Patent number 5,838,205
- Issue date Nov 17, 1998
- International Business Machines Corporation
- Frank David Ferraiolo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Delay equalization apparatus and method
- Patent number 5,825,226
- Issue date Oct 20, 1998
- International Business Machines Corporation
- Frank D. Ferraiolo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Fast locking variable frequency phase-locked loop
- Patent number 5,757,238
- Issue date May 26, 1998
- International Business Machines Corporation
- Frank David Ferraiolo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digitally controlled oscillator circuit
- Patent number 5,739,725
- Issue date Apr 14, 1998
- International Business Machines Corporation
- Frank David Ferraiolo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiple reference sense amplifier
- Patent number 5,729,159
- Issue date Mar 17, 1998
- International Business Machines Corporation
- John E. Gersbach
- G11 - INFORMATION STORAGE
Information Patent Grant
Phase-locked loop with charge distribution
- Patent number 5,724,008
- Issue date Mar 3, 1998
- International Business Machines Corporation
- Frank David Ferraiolo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Anti-latching mechanism for phase lock loops
- Patent number 5,694,087
- Issue date Dec 2, 1997
- International Business Machines Corporation
- Frank D. Ferraiolo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Band gap current reference circuit
- Patent number 5,694,032
- Issue date Dec 2, 1997
- International Business Machines Corporation
- John E. Gersbach
- G05 - CONTROLLING REGULATING
Information Patent Grant
System and method for calibrating damping factor or analog PLL
- Patent number 5,668,503
- Issue date Sep 16, 1997
- International Business Machines Corporation
- John Edwin Gersbach
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Switched capacitor current source
- Patent number 5,668,709
- Issue date Sep 16, 1997
- International Business Machine Corporation
- John Edwin Gersbach
- G05 - CONTROLLING REGULATING
Information Patent Grant
Self calibration segmented digital-to-analog converter
- Patent number 5,666,118
- Issue date Sep 9, 1997
- International Business Machines Corporation
- John Edwin Gersbach
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Self calibrating segmented digital-to-analog converter
- Patent number 5,642,116
- Issue date Jun 24, 1997
- International Business Machines Corporation
- John E. Gersbach
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Current reference circuit
- Patent number 5,635,869
- Issue date Jun 3, 1997
- International Business Machines Corporation
- Frank D. Ferraiolo
- G05 - CONTROLLING REGULATING
Information Patent Grant
Self-biased phase-locked loop
- Patent number 5,629,650
- Issue date May 13, 1997
- International Business Machines Corporation
- John E. Gersbach
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
All FET fully integrated current reference circuit
- Patent number 5,627,456
- Issue date May 6, 1997
- International Business Machines Corporation
- Ilya I. Novof
- G05 - CONTROLLING REGULATING
Information Patent Grant
Electrostatic discharge suppression circuit for integrated circuit...
- Patent number 5,598,313
- Issue date Jan 28, 1997
- International Business Machines Corporation
- John E. Gersbach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for calibrating damping factor of analog PLL
- Patent number 5,563,552
- Issue date Oct 8, 1996
- International Business Machines Corporation
- John E. Gersbach
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low distortion memory write current head drive
- Patent number 5,539,342
- Issue date Jul 23, 1996
- International Business Machines Corporation
- John E. Gersbach
- G11 - INFORMATION STORAGE
Information Patent Grant
Charge pump circuit with symmetrical current output for phase-contr...
- Patent number 5,508,660
- Issue date Apr 16, 1996
- International Business Machines Corporation
- John E. Gersbach
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Filter network for phase-locked loop circuit
- Patent number 5,504,459
- Issue date Apr 2, 1996
- International Business Machines Corporation
- John E. Gersbach
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Ring oscillator circuit having output with fifty percent duty cycle
- Patent number 5,485,126
- Issue date Jan 16, 1996
- International Business Machines Corporation
- John E. Gersbach
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
DC centering analog receiver for flash A/D converter
- Patent number 5,422,642
- Issue date Jun 6, 1995
- International Business Machines Corporation
- Paul W. Chung
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Line fault detection system with a differential driver
- Patent number 5,418,484
- Issue date May 23, 1995
- International Business Machines Corp.
- David W. Blum
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Fast communication link bit error rate estimator
- Patent number 5,418,789
- Issue date May 23, 1995
- International Business Machines Corporation
- John E. Gersbach
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

John E. Gersbach

Person

Patents Grantslast 30 patents

CVF current reference with standby mode

Slew rate control circuit

Low power voltage translation circuit

Pull-up and pull-down circuits

On-chip thermometry for control of chip operating temperature

Self-timed circuit having critical path timing detection

Variable-speed phase-locked loop system with on-the-fly switching a...

Delay equalization apparatus and method

Fast locking variable frequency phase-locked loop

Digitally controlled oscillator circuit

Multiple reference sense amplifier

Phase-locked loop with charge distribution

Anti-latching mechanism for phase lock loops

Band gap current reference circuit

System and method for calibrating damping factor or analog PLL

Switched capacitor current source

Self calibration segmented digital-to-analog converter

Self calibrating segmented digital-to-analog converter

Current reference circuit

Self-biased phase-locked loop

All FET fully integrated current reference circuit

Electrostatic discharge suppression circuit for integrated circuit...

System and method for calibrating damping factor of analog PLL

Low distortion memory write current head drive

Charge pump circuit with symmetrical current output for phase-contr...

Filter network for phase-locked loop circuit

Ring oscillator circuit having output with fifty percent duty cycle

DC centering analog receiver for flash A/D converter

Line fault detection system with a differential driver

Fast communication link bit error rate estimator