John E. Griffith

Person

Mahopac, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Wafer handler and methods of manufacture
- Patent number 10,049,909
- Issue date Aug 14, 2018
- GLOBALFOUNDRIES Inc.
- John J. Garant
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Controlling a discovery component, within a virtual environment, th...
- Patent number 9,866,547
- Issue date Jan 9, 2018
- International Business Machines Corporation
- John A. Griffith
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Wafer handler and methods of manufacture
- Patent number 9,613,842
- Issue date Apr 4, 2017
- GLOBALFOUNDRIES Inc.
- John J. Garant
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Controlling a discovery component, within a virtual environment, th...
- Patent number 9,497,187
- Issue date Nov 15, 2016
- International Business Machines Corporation
- John A. Griffith
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Reduction of edge chipping during wafer handling
- Patent number 8,807,184
- Issue date Aug 19, 2014
- International Business Machines Corporation
- Sarah H. Knickerbocker
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Reduction of edge chipping during wafer handling
- Patent number 8,753,460
- Issue date Jun 17, 2014
- International Business Machines Corporation
- Sarah H. Knickerbocker
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Interconnections for flip-chip using lead-free solders and having i...
- Patent number 8,314,500
- Issue date Nov 20, 2012
- Ultratech, Inc.
- Luc Belanger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnection for flip-chip using lead-free solders and having im...
- Patent number 7,932,169
- Issue date Apr 26, 2011
- International Business Machines Corporation
- Luc Belanger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming robust solder interconnect structures by reducing effects o...
- Patent number 7,767,575
- Issue date Aug 3, 2010
- Tessera Intellectual Properties, Inc.
- Kamalesh K. Srivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a bond pad on an I/C chip and resulting structure
- Patent number 7,572,726
- Issue date Aug 11, 2009
- International Business Machines Corporation
- Julie C. Biggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming robust solder interconnect structures by reducin...
- Patent number 7,473,997
- Issue date Jan 6, 2009
- International Business Machines Corporation
- Kamalesh K. Srivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for selective electroplating of semiconductor device I/O pad...
- Patent number 7,144,490
- Issue date Dec 5, 2006
- International Business Machines Corporation
- Tien-Jen Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming robust solder interconnect structures by reducin...
- Patent number 6,995,084
- Issue date Feb 7, 2006
- International Business Machines Corporation
- Kamalesh K. Srivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
I/C chip suitable for wire bonding
- Patent number 6,995,475
- Issue date Feb 7, 2006
- International Business Machines Corporation
- Julie C. Biggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Barrier for interconnect and method
- Patent number 6,992,389
- Issue date Jan 31, 2006
- International Business Machines Corporation
- Panayotis C. Andricacos
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reactive Ion Etching chamber design for flip chip interconnections
- Patent number 6,531,069
- Issue date Mar 11, 2003
- International Business Machines Corporation
- Kamalesh K. Srivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated method for etching of BLM titanium-tungsten alloys for C...
- Patent number 6,293,457
- Issue date Sep 25, 2001
- International Business Machines Corporation
- Kamalesh K. Srivastava
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method of measuring oxide thickness during semiconductor fabrication
- Patent number 6,228,665
- Issue date May 8, 2001
- International Business Machines Corporation
- Jonathan H. Griffith
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and apparatus for relieving stress and resisting stencil de...
- Patent number 5,277,749
- Issue date Jan 11, 1994
- International Business Machines Corporation
- Jonathan H. Griffith
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Process for etching composite chrome layers
- Patent number 4,588,471
- Issue date May 13, 1986
- International Business Machines Corporation
- Jonathan H. Griffith
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method and apparatus for calibrating a robot to compensate for inac...
- Patent number 4,362,977
- Issue date Dec 7, 1982
- International Business Machines Corporation
- Roger C. Evans
- B25 - HAND TOOLS PORTABLE POWER-DRIVEN TOOLS MANIPULATORS
Information Patent Grant
Method and apparatus for clamping a workpiece in a quasi-liquid medium
- Patent number 3,953,013
- Issue date Apr 27, 1976
- International Business Machines Corporation
- John E. Griffith
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
WAFER HANDLER AND METHODS OF MANUFACTURE
- Publication number 20170154800
- Publication date Jun 1, 2017
- GLOBALFOUNDRIES INC.
- John J. Garant
- B32 - LAYERED PRODUCTS
Information Patent Application
CONTROLLING A DISCOVERY COMPONENT, WITHIN A VIRTUAL ENVIRONMENT, TH...
- Publication number 20160359847
- Publication date Dec 8, 2016
- International Business Machines Corporation
- JOHN A. GRIFFITH
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CONTROLLING A DISCOVERY COMPONENT, WITHIN A VIRTUAL ENVIRONMENT, TH...
- Publication number 20160173487
- Publication date Jun 16, 2016
- International Business Machines Corporation
- JOHN A. GRIFFITH
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CONSTRUCTING VIRTUAL IMAGES FOR INTERDEPENDENT APPLICATIONS
- Publication number 20160139908
- Publication date May 19, 2016
- International Business Machines Corporation
- JOHN A. GRIFFITH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR CONSTRUCTING VIRTUAL IMAGES FOR INTERDEPENDENT APPLI...
- Publication number 20160139945
- Publication date May 19, 2016
- International Business Machines Corporation
- JOHN A. GRIFFITH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WAFER HANDLER AND METHODS OF MANUFACTURE
- Publication number 20150235891
- Publication date Aug 20, 2015
- International Business Machines Corporation
- John J. Garant
- B32 - LAYERED PRODUCTS
Information Patent Application
DISCOVERY AND GROUPING OF RELATED COMPUTING RESOURCES USING MACHINE...
- Publication number 20130290237
- Publication date Oct 31, 2013
- International Business Machines Corporation
- John A. Griffith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISCOVERY AND GROUPING OF RELATED COMPUTING RESOURCES USING MACHINE...
- Publication number 20130290238
- Publication date Oct 31, 2013
- International Business Machines Corporation
- John A. Griffith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCTION OF EDGE CHIPPING DURING WAFER HANDLING
- Publication number 20130164912
- Publication date Jun 27, 2013
- International Business Machines Corporation
- Sarah H. Knickerbocker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCTION OF EDGE CHIPPING DURING WAFER HANDLING
- Publication number 20130160705
- Publication date Jun 27, 2013
- International Business Machines Corporation
- Sarah H. Knickerbocker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEFECT CLOSURE
- Publication number 20130007526
- Publication date Jan 3, 2013
- International Business Machines Corporation
- Philip R. Riedel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCTION OF EDGE CHIPPING DURING WAFER HANDLING
- Publication number 20120193014
- Publication date Aug 2, 2012
- International Business Machines Corporation
- SARAH H. KNICKERBOCKER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Interconnection for flip-chip using lead-free solders and having im...
- Publication number 20100062597
- Publication date Mar 11, 2010
- Luc Belanger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMING ROBUST SOLDER INTERCONNECT STRUCTURES BY REDUCING EFFECTS O...
- Publication number 20090163019
- Publication date Jun 25, 2009
- International Business Machines Corporation
- Kamalesh K. Srivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECTIONS FOR FLIP-CHIP USING LEAD-FREE SOLDERS AND HAVING I...
- Publication number 20080157395
- Publication date Jul 3, 2008
- Luc Belanger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Device with area array pads for test probing
- Publication number 20060249854
- Publication date Nov 9, 2006
- Tien-Jen Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming a bond pad on an I/C chip and resulting structure
- Publication number 20060081981
- Publication date Apr 20, 2006
- International Business Machines Corporation
- Julie C. Biggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING ROBUST SOLDER INTERCONNECT STRUCTURES BY REDUCIN...
- Publication number 20060009022
- Publication date Jan 12, 2006
- International Business Machines Corporation
- Kamalesh K. Srivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BARRIER FOR INTERCONNECT AND METHOD
- Publication number 20050245070
- Publication date Nov 3, 2005
- International Business Machines Corporation
- Panayotis C. Andricacos
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING ROBUST SOLDER INTERCONNECT STRUCTURES BY REDUCIN...
- Publication number 20050208748
- Publication date Sep 22, 2005
- International Business Machines Corporation
- Kamalesh K. Srivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE WITH AREA ARRAY PADS FOR TEST PROBING
- Publication number 20050167837
- Publication date Aug 4, 2005
- International Business Machines Corporation
- Tien-Jen Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR SELECTIVE ELECTROPLATING OF SEMICONDUCTOR DEVICE I/O PAD...
- Publication number 20050103636
- Publication date May 19, 2005
- International Business Machines Corporation
- Tien-Jen Cheng
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Application
STABILIZING COPPER OVERLAYER FOR ENHANCED C4 INTERCONNECT RELIABILITY
- Publication number 20050104208
- Publication date May 19, 2005
- International Business Machines Corporation
- James C. Bartelo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming a bond pad on an I/C chip and resulting structure
- Publication number 20050062170
- Publication date Mar 24, 2005
- International Business Machines Corporation
- Julie C. Biggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ENCAPSULATED PIN STRUCTURE FOR IMPROVED RELIABILITY OF WAFER
- Publication number 20050026416
- Publication date Feb 3, 2005
- International Business Machines Corporation
- Tien-Jen Cheng
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Method of improving uniformity of etching of a film on an article
- Publication number 20020190028
- Publication date Dec 19, 2002
- International Business Machines Corporation
- Kamalesh K. Srivastava
- H01 - BASIC ELECTRIC ELEMENTS

John E. Griffith

Person

Patents Grantslast 30 patents

Wafer handler and methods of manufacture

Controlling a discovery component, within a virtual environment, th...

Wafer handler and methods of manufacture

Controlling a discovery component, within a virtual environment, th...

Reduction of edge chipping during wafer handling

Reduction of edge chipping during wafer handling

Interconnections for flip-chip using lead-free solders and having i...

Interconnection for flip-chip using lead-free solders and having im...

Forming robust solder interconnect structures by reducing effects o...

Method of forming a bond pad on an I/C chip and resulting structure

Method for forming robust solder interconnect structures by reducin...

Method for selective electroplating of semiconductor device I/O pad...

Method for forming robust solder interconnect structures by reducin...

I/C chip suitable for wire bonding

Barrier for interconnect and method

Reactive Ion Etching chamber design for flip chip interconnections

Integrated method for etching of BLM titanium-tungsten alloys for C...

Method of measuring oxide thickness during semiconductor fabrication

Methods and apparatus for relieving stress and resisting stencil de...

Process for etching composite chrome layers

Method and apparatus for calibrating a robot to compensate for inac...

Method and apparatus for clamping a workpiece in a quasi-liquid medium

Patents Applicationslast 30 patents

WAFER HANDLER AND METHODS OF MANUFACTURE

CONTROLLING A DISCOVERY COMPONENT, WITHIN A VIRTUAL ENVIRONMENT, TH...

CONTROLLING A DISCOVERY COMPONENT, WITHIN A VIRTUAL ENVIRONMENT, TH...

CONSTRUCTING VIRTUAL IMAGES FOR INTERDEPENDENT APPLICATIONS

TECHNIQUES FOR CONSTRUCTING VIRTUAL IMAGES FOR INTERDEPENDENT APPLI...

WAFER HANDLER AND METHODS OF MANUFACTURE

DISCOVERY AND GROUPING OF RELATED COMPUTING RESOURCES USING MACHINE...

DISCOVERY AND GROUPING OF RELATED COMPUTING RESOURCES USING MACHINE...

REDUCTION OF EDGE CHIPPING DURING WAFER HANDLING

REDUCTION OF EDGE CHIPPING DURING WAFER HANDLING

DEFECT CLOSURE

REDUCTION OF EDGE CHIPPING DURING WAFER HANDLING

Interconnection for flip-chip using lead-free solders and having im...

FORMING ROBUST SOLDER INTERCONNECT STRUCTURES BY REDUCING EFFECTS O...

INTERCONNECTIONS FOR FLIP-CHIP USING LEAD-FREE SOLDERS AND HAVING I...

Device with area array pads for test probing

Method of forming a bond pad on an I/C chip and resulting structure

METHOD FOR FORMING ROBUST SOLDER INTERCONNECT STRUCTURES BY REDUCIN...

BARRIER FOR INTERCONNECT AND METHOD

METHOD FOR FORMING ROBUST SOLDER INTERCONNECT STRUCTURES BY REDUCIN...

DEVICE WITH AREA ARRAY PADS FOR TEST PROBING

METHOD FOR SELECTIVE ELECTROPLATING OF SEMICONDUCTOR DEVICE I/O PAD...

STABILIZING COPPER OVERLAYER FOR ENHANCED C4 INTERCONNECT RELIABILITY

Method of forming a bond pad on an I/C chip and resulting structure

ENCAPSULATED PIN STRUCTURE FOR IMPROVED RELIABILITY OF WAFER

Method of improving uniformity of etching of a film on an article