Patent Application
20050026416
The field of the invention is that of integrated circuit packaging, in particular flip chip technology.
Printed circuit boards (also referred to as printed wiring boards), hereinafter simply referred to as a “PCB”, have become ubiquitous. PCB's typically are in the form of a dielectric substrate (such as for example an organic resin reinforced by fibers) which is cladded on one or both sides with a conductor (such as for example copper). The dielectric substrate is provided with a predetermined pattern of perforations for making connections with wiring and electrical devices, wherein the conductor is patterned so as to provide a predetermined electrical routing between the perforations so that the wiring and electrical devices are functionally interconnected.
During the 1960's IBM Corporation developed an alternative technology to hardwiring all interfaces, referred to commonly as “controlled collapse chip connection” or simply “C4”. According to this technology, a chip is attached to the electronics of a PCB by matched contact of bumps on the chip with interface pads on the PCB. A chip provided with a series of bumps for C4 is referred to as a “flip chip”. The bumps have been typically a solder alloy (for example lead 97%, tin 3%) deposited by a bump mask onto wettable bump pads, and the interface pads on the PCB are also wettable whereby electrical and mechanical interconnections are formed simultaneously by reflowing of the bumps. Advantages of this technology include the reflowing compensating for chip-to-substrate misalignment incurred during chip placement and for the bumps to absorb stress.
The bumps are deposited onto the bump pads using a bump mask which is then removed. At this stage, the bumps resemble a truncated cone, being widest at the bump pad. Thereafter, a non; oxidizing reflow process is applied to the bumps, whereafter the bumps are convexly shaped, resembling truncated egg-shapes.
While C4 technology may be used to provide bumps on the chip, as was detailed hereinabove, it is to be noted that C4 technology may be equally well practiced to provide bumps on the PCB, wherein the chip is provided with the interface pads. Further, C4 technology may be practiced for attaching electronic structures other than chips; e.g. small PCBs attached to larger ones, etc.
As dimensions shrink, it is required to reduce the pitch and pack more contacts within a given area. That, in turn, reduces the permissible spacing between C4 bumps and increases the chances of shorting adjacent bumps. Various attempts have been made to increase contact density.
US2002-0179689 A1: Pillar Connections for Semiconductor Chips and Method of Manufacture (Inventor: F. Tung) shows a copper pillar capped by a eutectic solder. The structure is formed by sequentially plating stacks of metallurgy The copper pin is exposed to and is in contact with the solder, thereby permitting the formation of undesirable Cu—Sn intermetallic compounds.
U.S. Pat. No. 5,773,889: Wire Interconnect Structures for Connecting an Integrated Circuit to a Substrate (Inventor D. Love, et al.) shows the fabrication of a pin-like structure of copper partially by a shell of nickel. Devices are connected to substrates by fillets of solder at both bases of the pin structure. This structure is complex, requiring the use of three masks.
The invention relates to a method of making fine-pitch conductive pads (also referred to as bumps) for flip-chip bonding.
A feature of the invention is a supporting pin plated directly to a seed layer.
Another feature of the invention is plating the pin through an aperture defined by lithography in a layer of photoreresist.
Another feature of the invention is selective etching of the seed stack selective to the solder, removing the seed stack without attacking the solder.
Boxes 35 represent schematically vias extending up from interconnections not shown through the polyimide. The contacts on the top of the structure will be made to these vias.
Layer 20 is a barrier and/or adhesion metallurgy layer. For example, TiW, Ti, TaN and other materials known to those skilled in the art are used to block penetration of the contact materials, e.g. copper and/or to promote adhesion between the contact materials and the interconnect materials, (typically aluminum alloys).
Layer 10 is a seed layer that promotes deposition and plating of the material for the pins to be formed. As the contacts become smaller, the current capacity of the contact materials becomes more important, so that copper is preferred is the material.
Advantageously, the copper in the pins 60 is bonded directly to the copper in seed layer 10. In prior art structures, the pins were attached by solder fillets, which had the drawback of having direct contact between the copper and the solder.
As dimensions shrink, the thickness of the various layers will be adjusted accordingly.
Layer 85 will be plated or deposited after the step of forming the barrier layer and before the step of depositing the solder.
The following summarizes the sequence of process steps.
Process Sequence
1. Starting structure: integrated circuit with terminals below apertures in an insulator (polyimide); seed metal stack.
2. pattern photoresist to define pin base.
3. etch seed layers, leaving pads.
4. pattern thick photoresist for pins.
5. plate pins in apertures.
6. strip photoresist.
7. plate barrier material on pins and pad.
8. plate barrier selectively to solder.
9. etch seed stack selective to solder and barrier.
10. reflow solder.
Those skilled in the art will readily be able to adapt the foregoing example to other circumstances. For example, the terms forming, depositing and plating are not meant to be exclusive and are meant to include alternative methods, such as sputtering, chemical vapor deposition, etc. to achieve the same or similar result.
While the invention has been described in terms of a single preferred embodiment, those skilled in the art will recognize that the invention can be practiced in various versions within the spirit and scope of the following claims.
