John Hogeboom

Person

Ottawa, CA

People

Patents Grantslast 30 patents

Information Patent Grant
S12 TX FIR architecture
- Patent number 9,405,511
- Issue date Aug 2, 2016
- STMicroelectronics (Canada) Inc.
- John Hogeboom
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
S12 TX FIR architecture
- Patent number 8,886,694
- Issue date Nov 11, 2014
- STMicroelectronics (Canada) Inc.
- John Hogeboom
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Fractional divider for avoidance of LC-VCO interference and jitter
- Patent number 8,754,682
- Issue date Jun 17, 2014
- STMicroelectronics (Canada) Inc.
- John Hogeboom
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Parallel closed-loop DFE filter architecture
- Patent number 8,731,041
- Issue date May 20, 2014
- STMicroelectronics (Canada) Inc.
- Anton Pelteshki
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
SERDES with jitter-based built-in self test (BIST) for adapting FIR...
- Patent number 8,228,972
- Issue date Jul 24, 2012
- STMicroelectronics, Inc.
- Davide Tonietto
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Sample-and-hold circuit with current gain
- Patent number 4,233,528
- Issue date Nov 11, 1980
- Northern Telecom Limited
- John G. Hogeboom
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
S12 TX FIR ARCHITECTURE
- Publication number 20150074160
- Publication date Mar 12, 2015
- STMicroelectronics (Canada), Inc.
- JOHN HOGEBOOM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Parallel Closed-Loop DFE Filter Architecture
- Publication number 20120269255
- Publication date Oct 25, 2012
- STMicroelectronics (Canada) Inc.
- Anton Pelteshki
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
BANG-BANG OFFSET CANCELLATION (AUTOZERO)
- Publication number 20120269305
- Publication date Oct 25, 2012
- STMicroelectronics (Canada) Inc.
- John Hogeboom
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
FRACTIONAL DIVIDER FOR AVOIDANCE OF LC-VCO INTERFERENCE AND JITTER
- Publication number 20120268177
- Publication date Oct 25, 2012
- STMicroelectronics (Canada) Inc.
- John Hogeboom
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CENTRAL LC PLL WITH INJECTION LOCKED RING PLL OR DELL PER LANE
- Publication number 20120161827
- Publication date Jun 28, 2012
- STMicroelectronics (Canada) Inc.
- Paul Madeira
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
S12 TX FIR ARCHITECTURE
- Publication number 20120166505
- Publication date Jun 28, 2012
- STMicroelectronics S.r.l.
- John Hogeboom
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EYE MAPPING BUILT-IN SELF TEST (BIST) METHOD AND APPARATUS
- Publication number 20100097087
- Publication date Apr 22, 2010
- STMicroelectronics, Inc.
- John Hogeboom
- G01 - MEASURING TESTING
Information Patent Application
SERDES WITH JITTER-BASED BUILT-IN SELF TEST (BIST) FOR ADAPTING FIR...
- Publication number 20090304054
- Publication date Dec 10, 2009
- STMicroelectronics, Inc.
- Davide Tonietto
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

John Hogeboom

Person

Patents Grantslast 30 patents

S12 TX FIR architecture

S12 TX FIR architecture

Fractional divider for avoidance of LC-VCO interference and jitter

Parallel closed-loop DFE filter architecture

SERDES with jitter-based built-in self test (BIST) for adapting FIR...

Sample-and-hold circuit with current gain

Patents Applicationslast 30 patents

S12 TX FIR ARCHITECTURE

Parallel Closed-Loop DFE Filter Architecture

BANG-BANG OFFSET CANCELLATION (AUTOZERO)

FRACTIONAL DIVIDER FOR AVOIDANCE OF LC-VCO INTERFERENCE AND JITTER

CENTRAL LC PLL WITH INJECTION LOCKED RING PLL OR DELL PER LANE

S12 TX FIR ARCHITECTURE

EYE MAPPING BUILT-IN SELF TEST (BIST) METHOD AND APPARATUS

SERDES WITH JITTER-BASED BUILT-IN SELF TEST (BIST) FOR ADAPTING FIR...