John J. Seliskar

Person

Colorado Springs, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Low threshold voltage MOS transistor and method of manufacture
- Patent number 6,525,377
- Issue date Feb 25, 2003
- LSI Logic Corporation
- John J. Seliskar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Subtractive oxidation method of fabricating a short-length and vert...
- Patent number 6,355,532
- Issue date Mar 12, 2002
- LSI Logic Corporation
- John J. Seliskar
- B82 - NANO-TECHNOLOGY
Information Patent Grant
MeV implantation to form vertically modulated N+ buried lay...
- Patent number 6,316,817
- Issue date Nov 13, 2001
- LSI Logic Corporation
- John J. Seliskar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit device and method of making the same using chemi...
- Patent number 6,284,586
- Issue date Sep 4, 2001
- LSI Logic Corporation
- John J. Seliskar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit device having a capacitor with the dielectric pe...
- Patent number 6,115,233
- Issue date Sep 5, 2000
- LSI Logic Corporation
- John J. Seliskar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low threshold voltage MOS transistor and method of manufacture
- Patent number 5,985,705
- Issue date Nov 16, 1999
- LSI Logic Corporation
- John J. Seliskar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Use of MEV implantation to form vertically modulated N+ buried laye...
- Patent number 5,858,828
- Issue date Jan 12, 1999
- Symbios, Inc.
- John J. Seliskar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for fabricating a moderate-depth diffused emitter bipolar t...
- Patent number 5,780,329
- Issue date Jul 14, 1998
- Symbios, Inc.
- Todd A. Randazzo
- H01 - BASIC ELECTRIC ELEMENTS

John J. Seliskar

Person

Patents Grantslast 30 patents

Low threshold voltage MOS transistor and method of manufacture

Subtractive oxidation method of fabricating a short-length and vert...

MeV implantation to form vertically modulated N&#x0002B; buried lay...

Integrated circuit device and method of making the same using chemi...

Integrated circuit device having a capacitor with the dielectric pe...

Low threshold voltage MOS transistor and method of manufacture

Use of MEV implantation to form vertically modulated N+ buried laye...

Process for fabricating a moderate-depth diffused emitter bipolar t...

MeV implantation to form vertically modulated N+ buried lay...