John J. Zasio

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Wafer-level burn-in
- Patent number 6,337,576
- Issue date Jan 8, 2002
- Alpine Microsystems, Inc.
- Andrew K. Wiggin
- G01 - MEASURING TESTING
Information Patent Grant
Module and method for interconnecting integrated circuits that faci...
- Patent number 6,300,161
- Issue date Oct 9, 2001
- Alpine Microsystems, Inc.
- Martin P. Goetz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS buffer circuit having power-down feature
- Patent number 5,570,036
- Issue date Oct 29, 1996
- HaL Computer Systems, Inc.
- Robert K. Montoye
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
CMOS buffer circuit having increased speed
- Patent number 5,541,528
- Issue date Jul 30, 1996
- HaL Computer Systems, Inc.
- Robert K. Montoye
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Cellular integrated circuit and hierarchical method
- Patent number 5,095,356
- Issue date Mar 10, 1992
- Fujitsu Limited
- Hisashige Ando
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Cellular integrated circuit and hierarchial method
- Patent number 4,969,029
- Issue date Nov 6, 1990
- Fujitsu Limited
- Hisashige Ando
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Simulation system
- Patent number 4,937,770
- Issue date Jun 26, 1990
- Teradyne, Inc.
- Michael W. Samuels
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Static timing analysis of semiconductor digital circuits
- Patent number 4,924,430
- Issue date May 8, 1990
- Teradyne, Inc.
- John J. Zasio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for scan testing CMOS integrated systems
- Patent number 4,782,283
- Issue date Nov 1, 1988
- AIDA Corporation
- John J. Zasio
- G01 - MEASURING TESTING
Information Patent Grant
CMOS multiport general purpose register
- Patent number 4,737,933
- Issue date Apr 12, 1988
- Storage Technology Partners
- Michael Chiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay testing method for CMOS LSI and VLSI integrated circuits
- Patent number 4,587,480
- Issue date May 6, 1986
- Storage Technology Partners
- John J. Zasio
- G11 - INFORMATION STORAGE
Information Patent Grant
System for detecting and correcting errors in a CMOS computer system
- Patent number 4,553,236
- Issue date Nov 12, 1985
- Storage Technology Partners
- John J. Zasio
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Test fixture for providing electrical access to each I/O pin of a V...
- Patent number 4,504,783
- Issue date Mar 12, 1985
- Storage Technology Partners
- John Zasio
- G01 - MEASURING TESTING
Information Patent Grant
CMOS scannable latch
- Patent number 4,495,629
- Issue date Jan 22, 1985
- Storage Technology Partners
- John J. Zasio
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
CMOS LSI and VLSI chips having internal delay testing capability
- Patent number 4,495,628
- Issue date Jan 22, 1985
- Storage Technology Partners
- John J. Zasio
- G11 - INFORMATION STORAGE
Information Patent Grant
Discharge device and method for use in processing semiconductor dev...
- Patent number 4,458,129
- Issue date Jul 3, 1984
- Fujitsu, Limited
- John J. Zasio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for calibrating electron beam systems
- Patent number 4,442,361
- Issue date Apr 10, 1984
- Storage Technology Partners (through STC Computer Research Corporation)
- John Zasio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of aligning electron beam apparatus
- Patent number 4,420,691
- Issue date Dec 13, 1983
- Fujitsu Limited
- John J. Zasio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS Circuit using transmission line interconnections
- Patent number 4,414,480
- Issue date Nov 8, 1983
- Storage Technology Partners
- John J. Zasio
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
LSI Chip package and method
- Patent number 4,396,971
- Issue date Aug 2, 1983
- Amdahl Corporation
- Robert J. Beall
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Discharge device and method for use in processing semiconductor dev...
- Patent number 4,350,866
- Issue date Sep 21, 1982
- Fujitsu Limited
- John J. Zasio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Table positioning system including optical reference position measu...
- Patent number 4,191,916
- Issue date Mar 4, 1980
- Fujitsu Limited
- John J. Zasio
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Large-scale integrated circuit with integral bi-directional test ci...
- Patent number 4,180,772
- Issue date Dec 25, 1979
- Fujitsu Limited
- Fred K. Buelow
- G01 - MEASURING TESTING
Information Patent Grant
Electron beam exposure system method and apparatus
- Patent number 4,147,937
- Issue date Apr 3, 1979
- Fujitsu Limited
- Fred K. Buelow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Overlapping boundary electron exposure system method and apparatus
- Patent number 4,132,898
- Issue date Jan 2, 1979
- Fujitsu Limited
- Fred K. Buelow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
LSI Chip package and method
- Patent number 4,115,837
- Issue date Sep 19, 1978
- Amdahl Corporation
- Robert J. Beall
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density multilayer printed circuit card assembly and method
- Patent number 4,016,463
- Issue date Apr 5, 1977
- Amdahl Corporation
- Robert J. Beall
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
LSI chip construction and method
- Patent number 3,981,070
- Issue date Sep 21, 1976
- Amdahl Corporation
- Fred K. Buelow
- H01 - BASIC ELECTRIC ELEMENTS

John J. Zasio

Person

Patents Grantslast 30 patents

Wafer-level burn-in

Module and method for interconnecting integrated circuits that faci...

CMOS buffer circuit having power-down feature

CMOS buffer circuit having increased speed

Cellular integrated circuit and hierarchical method

Cellular integrated circuit and hierarchial method

Simulation system

Static timing analysis of semiconductor digital circuits

Apparatus for scan testing CMOS integrated systems

CMOS multiport general purpose register

Delay testing method for CMOS LSI and VLSI integrated circuits

System for detecting and correcting errors in a CMOS computer system

Test fixture for providing electrical access to each I/O pin of a V...

CMOS scannable latch

CMOS LSI and VLSI chips having internal delay testing capability

Discharge device and method for use in processing semiconductor dev...

System and method for calibrating electron beam systems

Method of aligning electron beam apparatus

CMOS Circuit using transmission line interconnections

LSI Chip package and method

Discharge device and method for use in processing semiconductor dev...

Table positioning system including optical reference position measu...

Large-scale integrated circuit with integral bi-directional test ci...

Electron beam exposure system method and apparatus

Overlapping boundary electron exposure system method and apparatus

LSI Chip package and method

High density multilayer printed circuit card assembly and method

LSI chip construction and method