John MacPherson

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Vertical fuse structure for integrated circuits containing an expos...
- Patent number 6,486,527
- Issue date Nov 26, 2002
- John MacPherson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical fuse structure for integrated circuits and a method of dis...
- Patent number 6,369,437
- Issue date Apr 9, 2002
- Clear Logic, Inc.
- John MacPherson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sacrificial bond pads for laser configured integrated circuits
- Patent number 6,348,742
- Issue date Feb 19, 2002
- Clear Logic, Inc.
- John MacPherson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Designing integrated circuit gate arrays using programmable logic d...
- Patent number 6,311,316
- Issue date Oct 30, 2001
- Clear Logic, Inc.
- Alan H. Huggins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modified lead frame for improved parallelism of a die to package
- Patent number 6,239,480
- Issue date May 29, 2001
- Clear Logic, Inc.
- John MacPherson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of improving parallelism of a die to package using a modifie...
- Patent number 6,235,556
- Issue date May 22, 2001
- Clear Logic, Inc.
- John MacPherson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Inter-conductive layer fuse for integrated circuits
- Patent number 6,096,566
- Issue date Aug 1, 2000
- Clear Logic, Inc.
- John MacPherson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Using microspheres as a stress buffer for integrated circuit protot...
- Patent number 6,087,200
- Issue date Jul 11, 2000
- Clear Logic, Inc.
- John MacPherson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Inter-conductive layer fuse for integrated circuits
- Patent number 6,078,091
- Issue date Jun 20, 2000
- Clear Logic, Inc.
- John MacPherson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of customizing integrated circuits by selective secondary de...
- Patent number 6,060,330
- Issue date May 9, 2000
- Clear Logic, Inc.
- Alan H. Huggins
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Die structure using microspheres as a stress buffer for integrated...
- Patent number 6,020,648
- Issue date Feb 1, 2000
- Clear Logic, Inc.
- John MacPherson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of customizing integrated circuits by depositing two resist...
- Patent number 5,989,783
- Issue date Nov 23, 1999
- Clear Logic, Inc.
- Alan H. Huggins
- B65 - CONVEYING PACKING STORING HANDLING THIN OR FILAMENTARY MATERIAL
Information Patent Grant
Method of customizing integrated circuits using standard masks and...
- Patent number 5,985,518
- Issue date Nov 16, 1999
- Clear Logic, Inc.
- Alan H. Huggins
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making a reusable photolithography mask
- Patent number 5,945,238
- Issue date Aug 31, 1999
- Clear Logic, Inc.
- Alan H. Huggins
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method of customizing integrated circuits by selective secondary de...
- Patent number 5,885,749
- Issue date Mar 23, 1999
- Clear Logic, Inc.
- Alan H. Huggins
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Apparatus and method for measuring the gripping strength of a vacuu...
- Patent number 5,783,754
- Issue date Jul 21, 1998
- Integrated Device Technology, Inc.
- John MacPherson
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
METHODS AND SYSTEMS FOR DESIGNING INTEGRATED CIRCUIT GATE ARRAYS
- Publication number 20030200520
- Publication date Oct 23, 2003
- Alan H. Huggins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Vertical fuse structure for integrated circuits and a method of dis...
- Publication number 20020100958
- Publication date Aug 1, 2002
- CLEAR LOGIC, INC.
- John MacPherson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SACRIFICIAL BOND PADS FOR LASER CONFIGURED INTEGRATED CIRCUITS
- Publication number 20020017729
- Publication date Feb 14, 2002
- JOHN MACPHERSON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Customization of an integrated circuit in packaged form
- Publication number 20010023118
- Publication date Sep 20, 2001
- John MacPherson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of improving parallelism of a die to package using a modifie...
- Publication number 20010000210
- Publication date Apr 12, 2001
- John MacPherson
- H01 - BASIC ELECTRIC ELEMENTS

John MacPherson

Person

Patents Grantslast 30 patents

Vertical fuse structure for integrated circuits containing an expos...

Vertical fuse structure for integrated circuits and a method of dis...

Sacrificial bond pads for laser configured integrated circuits

Designing integrated circuit gate arrays using programmable logic d...

Modified lead frame for improved parallelism of a die to package

Method of improving parallelism of a die to package using a modifie...

Inter-conductive layer fuse for integrated circuits

Using microspheres as a stress buffer for integrated circuit protot...

Inter-conductive layer fuse for integrated circuits

Method of customizing integrated circuits by selective secondary de...

Die structure using microspheres as a stress buffer for integrated...

Method of customizing integrated circuits by depositing two resist...

Method of customizing integrated circuits using standard masks and...

Method of making a reusable photolithography mask

Method of customizing integrated circuits by selective secondary de...

Apparatus and method for measuring the gripping strength of a vacuu...

Patents Applicationslast 30 patents

METHODS AND SYSTEMS FOR DESIGNING INTEGRATED CIRCUIT GATE ARRAYS

Vertical fuse structure for integrated circuits and a method of dis...

SACRIFICIAL BOND PADS FOR LASER CONFIGURED INTEGRATED CIRCUITS

Customization of an integrated circuit in packaged form

Method of improving parallelism of a die to package using a modifie...