John Mahoney

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Configurable parallel and bit serial load apparatus
- Patent number 5,995,988
- Issue date Nov 30, 1999
- Xilinx, Inc.
- Philip M. Freidin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configurable parallel and bit serial load apparatus
- Patent number 5,961,576
- Issue date Oct 5, 1999
- Xilinx, Inc.
- Philip M. Freidin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configurable parallel and bit serial load apparatus
- Patent number 5,844,829
- Issue date Dec 1, 1998
- Xilinx, Inc.
- Philip M. Freidin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configurable parallel and bit serial load apparatus
- Patent number 5,742,531
- Issue date Apr 21, 1998
- Philip M. Freidin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Deskewed clock distribution network with edge clock
- Patent number 5,712,579
- Issue date Jan 27, 1998
- Xilinx, Inc.
- Khue Duong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Fast pipeline frame full detector
- Patent number 5,694,056
- Issue date Dec 2, 1997
- Xilinx, Inc.
- John E. Mahoney
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Structure and method for programming antifuses in an integrated cir...
- Patent number 5,367,207
- Issue date Nov 22, 1994
- Xilinx, Inc.
- F. Erich Goetting
- G11 - INFORMATION STORAGE
Information Patent Grant
System for scan testing of logic circuit networks
- Patent number 5,155,432
- Issue date Oct 13, 1992
- Xilinx, Inc.
- John E. Mahoney
- G01 - MEASURING TESTING
Information Patent Grant
Structure and method for producing mask-programmed integrated circu...
- Patent number 5,068,603
- Issue date Nov 26, 1991
- Xilinx, Inc.
- John E. Mahoney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for scan testing of logic circuit networks
- Patent number 5,047,710
- Issue date Sep 10, 1991
- Xilinx, Inc.
- John E. Mahoney
- G01 - MEASURING TESTING
Information Patent Grant
System for scan testing of logic circuit networks
- Patent number 4,855,669
- Issue date Aug 8, 1989
- Xilinx, Inc.
- John E. Mahoney
- G01 - MEASURING TESTING
Information Patent Grant
CMOS power-on reset circuit
- Patent number 4,746,822
- Issue date May 24, 1988
- Xilinx, Inc.
- John Mahoney
- H03 - BASIC ELECTRONIC CIRCUITRY

John Mahoney

Person

Patents Grantslast 30 patents

Configurable parallel and bit serial load apparatus

Configurable parallel and bit serial load apparatus

Configurable parallel and bit serial load apparatus

Configurable parallel and bit serial load apparatus

Deskewed clock distribution network with edge clock

Fast pipeline frame full detector

Structure and method for programming antifuses in an integrated cir...

System for scan testing of logic circuit networks

Structure and method for producing mask-programmed integrated circu...

System for scan testing of logic circuit networks

System for scan testing of logic circuit networks

CMOS power-on reset circuit