John Wuu

Person

Ft Collins, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
ECC optimization
- Patent number 12,212,337
- Issue date Jan 28, 2025
- Xilinx, Inc.
- Kumar Rahul
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
SRAM power savings and write assist
- Patent number 12,165,700
- Issue date Dec 10, 2024
- Advanced Micro Devices, Inc.
- Russell J. Schreiber
- G11 - INFORMATION STORAGE
Information Patent Grant
Through-silicon via layout for multi-die integrated circuits
- Patent number 12,107,076
- Issue date Oct 1, 2024
- Advanced Micro Devices, Inc.
- Wonjun Jung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual read port latch array bitcell
- Patent number 12,073,919
- Issue date Aug 27, 2024
- Advanced Micro Devices, Inc.
- Arijit Banerjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single event upset tolerant memory device
- Patent number 12,045,469
- Issue date Jul 23, 2024
- Xilinx, Inc.
- Kumar Rahul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Split read port latch array bit cell
- Patent number 12,033,721
- Issue date Jul 9, 2024
- Advanced Micro Devices, Inc.
- Arijit Banerjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stacked die circuit routing system and method
- Patent number 11,869,874
- Issue date Jan 9, 2024
- Advanced Micro Devices, Inc.
- John Wuu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low power cache
- Patent number 11,822,484
- Issue date Nov 21, 2023
- Advanced Micro Devices, Inc.
- Vydhyanathan Kalyanasundharam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scheme for enabling die reuse in 3D stacked products
- Patent number 11,804,479
- Issue date Oct 31, 2023
- Advanced Micro Devices, Inc.
- John J. Wuu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Latch bit cells
- Patent number 11,715,514
- Issue date Aug 1, 2023
- Advanced Micro Devices, Inc.
- Russell J. Schreiber
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual-track bitline scheme for 6T SRAM cells
- Patent number 11,710,698
- Issue date Jul 25, 2023
- Advanced Micro Devices, Inc.
- John J. Wuu
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with expandable row width
- Patent number 11,676,659
- Issue date Jun 13, 2023
- Advanced Micro Devices, Inc.
- John Wuu
- G11 - INFORMATION STORAGE
Information Patent Grant
Write masked latch bit cell
- Patent number 11,610,627
- Issue date Mar 21, 2023
- Advanced Micro Devices, Inc.
- Russell J. Schreiber
- G11 - INFORMATION STORAGE
Information Patent Grant
Hybrid library latch array
- Patent number 11,527,270
- Issue date Dec 13, 2022
- Advanced Micro Devices, Inc.
- John J. Wuu
- G11 - INFORMATION STORAGE
Information Patent Grant
Folded cell layout for 6T SRAM cell
- Patent number 11,437,316
- Issue date Sep 6, 2022
- Advanced Micro Devices, Inc.
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
In memory logic functions using memory arrays
- Patent number 11,233,510
- Issue date Jan 25, 2022
- Advanced Micro Devices, Inc.
- John J. Wuu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory with expandable row width
- Patent number 11,205,477
- Issue date Dec 21, 2021
- Advanced Micro Devices, Inc.
- John Wuu
- G11 - INFORMATION STORAGE
Information Patent Grant
Arrangement and thermal management of 3D stacked dies
- Patent number 11,189,540
- Issue date Nov 30, 2021
- Advanced Micro Devices, Inc.
- John Wuu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Arrangement and thermal management of 3D stacked dies
- Patent number 11,164,807
- Issue date Nov 2, 2021
- Advanced Micro Devices, Inc.
- John Wuu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Timer for use dual voltage supplies
- Patent number 10,839,875
- Issue date Nov 17, 2020
- Advanced Micro Devices, Inc.
- Srinivas R. Sathu
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with expandable row width
- Patent number 10,783,953
- Issue date Sep 22, 2020
- Advanced Micro Devices, Inc.
- John Wuu
- G11 - INFORMATION STORAGE
Information Patent Grant
Flexibile interfaces using through-silicon via technology
- Patent number 10,644,826
- Issue date May 5, 2020
- Advanced Micro Devices, Inc.
- John Wuu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Configuration of multi-die modules with through-silicon vias
- Patent number 10,509,752
- Issue date Dec 17, 2019
- Advanced Micro Devices, Inc.
- Russell Schreiber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Arrangement and thermal management of 3D stacked dies
- Patent number 10,431,517
- Issue date Oct 1, 2019
- Advanced Micro Devices, Inc.
- John Wuu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable write word line boost for low voltage memory operation
- Patent number 10,366,734
- Issue date Jul 30, 2019
- Advanced Micro Devices, Inc.
- Alexander W. Schaefer
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory including side-car arrays with irregular sized entries
- Patent number 10,311,191
- Issue date Jun 4, 2019
- Advanced Micro Devices, Inc.
- John J. Wuu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Swizzling in 3D stacked memory
- Patent number 10,303,398
- Issue date May 28, 2019
- Advanced Micro Devices, Inc.
- John Wuu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
VSS bitcell sleep scheme involving modified bitcell for terminating...
- Patent number 10,043,572
- Issue date Aug 7, 2018
- Advanced Micro Devices, Inc.
- Russell Schreiber
- G11 - INFORMATION STORAGE
Information Patent Grant
Pseudo-dynamic circuit for multi-voltage timing interlocks
- Patent number 9,953,687
- Issue date Apr 24, 2018
- Advanced Micro Devices, Inc.
- John J. Wuu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Sidecar SRAM for high granularity in floor plan aspect ratio
- Patent number 9,575,891
- Issue date Feb 21, 2017
- Advanced Micro Devices, Inc.
- John R. Riley
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
ECC OPTIMIZATION
- Publication number 20240333307
- Publication date Oct 3, 2024
- Xilinx, Inc.
- Kumar RAHUL
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DIE PAIR DEVICE PARTITIONING
- Publication number 20240324247
- Publication date Sep 26, 2024
- ADVANCED MICRO DEVICES, INC.
- Samuel Naffziger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADVANCED PROCESS IN PROCESS PAIR WITHOUT FUSES
- Publication number 20240324248
- Publication date Sep 26, 2024
- ADVANCED MICRO DEVICES, INC.
- John Wuu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TEMPERATURE SENSORS IN DIE PAIR TOPOLOGY
- Publication number 20240321668
- Publication date Sep 26, 2024
- ADVANCED MICRO DEVICES, INC.
- Thomas D. Burd
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BACKSIDE POWER
- Publication number 20240321702
- Publication date Sep 26, 2024
- ADVANCED MICRO DEVICES, INC.
- Yan Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THERMALLY AWARE STACKING TOPOLOGY
- Publication number 20240321827
- Publication date Sep 26, 2024
- ADVANCED MICRO DEVICES, INC.
- Omar Zia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BACK END OF LINE OPTIMIZED TO FUNCTION IN A 3D STACK CONFIGURATION
- Publication number 20240321706
- Publication date Sep 26, 2024
- ADVANCED MICRO DEVICES, INC.
- William George En
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SINGLE EVENT UPSET TOLERANT MEMORY DEVICE
- Publication number 20240201863
- Publication date Jun 20, 2024
- Xilinx, Inc.
- Kumar RAHUL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BACKSIDE POWER DELIVERY AND POWER GRID PATTERN TO SUPPORT 3D DIE ST...
- Publication number 20240105675
- Publication date Mar 28, 2024
- ADVANCED MICRO DEVICES, INC.
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SCHEME FOR ENABLING DIE REUSE IN 3D STACKED PRODUCTS
- Publication number 20240063206
- Publication date Feb 22, 2024
- ADVANCED MICRO DEVICES, INC.
- John J. Wuu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKING SEMICONDUCTOR DEVICES BY BONDING FRONT SURFACES OF DIFFERE...
- Publication number 20230268319
- Publication date Aug 24, 2023
- ADVANCED MICRO DEVICES, INC.
- RAHUL AGARWAL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THROUGH-SILICON VIA LAYOUT FOR MULTI-DIE INTEGRATED CIRCUITS
- Publication number 20230207527
- Publication date Jun 29, 2023
- ADVANCED MICRO DEVICES, INC.
- Wonjun JUNG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW POWER CACHE
- Publication number 20230195642
- Publication date Jun 22, 2023
- ADVANCED MICRO DEVICES, INC.
- Vydhyanathan Kalyanasundharam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC SETUP AND HOLD TIMES ADJUSTMENT FOR MEMORIES
- Publication number 20230112432
- Publication date Apr 13, 2023
- ADVANCED MICRO DEVICES, INC.
- John J. Wuu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SRAM POWER SAVINGS AND WRITE ASSIST
- Publication number 20230100607
- Publication date Mar 30, 2023
- ADVANCED MICRO DEVICES, INC.
- Russell J. Schreiber
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-DIE COMMUNICATIONS COUPLINGS USING A SINGLE BRIDGE DIE
- Publication number 20230069294
- Publication date Mar 2, 2023
- ADVANCED MICRO DEVICES, INC.
- RAHUL AGARWAL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL READ PORT LATCH ARRAY BITCELL
- Publication number 20220415377
- Publication date Dec 29, 2022
- ADVANCED MICRO DEVICES, INC.
- Arijit Banerjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPLIT READ PORT LATCH ARRAY BIT CELL
- Publication number 20220415378
- Publication date Dec 29, 2022
- ADVANCED MICRO DEVICES, INC.
- Arijit Banerjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID LIBRARY LATCH ARRAY
- Publication number 20220366945
- Publication date Nov 17, 2022
- ADVANCED MICRO DEVICES, INC.
- John J. Wuu
- G11 - INFORMATION STORAGE
Information Patent Application
WRITE MASKED LATCH BIT CELL
- Publication number 20220358996
- Publication date Nov 10, 2022
- ADVANCED MICRO DEVICES, INC.
- Russell J. Schreiber
- G11 - INFORMATION STORAGE
Information Patent Application
LATCH BIT CELLS
- Publication number 20220359015
- Publication date Nov 10, 2022
- ADVANCED MICRO DEVICES, INC.
- Russell J. Schreiber
- G11 - INFORMATION STORAGE
Information Patent Application
STACKED DIE CIRCUIT ROUTING SYSTEM AND METHOD
- Publication number 20220189921
- Publication date Jun 16, 2022
- ADVANCED MICRO DEVICES, INC.
- John WUU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY WITH EXPANDABLE ROW WIDTH
- Publication number 20220148650
- Publication date May 12, 2022
- ADVANCED MICRO DEVICES, INC.
- John WUU
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL-TRACK BITLINE SCHEME FOR 6T SRAM CELLS
- Publication number 20220093503
- Publication date Mar 24, 2022
- ADVANCED MICRO DEVICES, INC.
- John J. Wuu
- G11 - INFORMATION STORAGE
Information Patent Application
FOLDED CELL LAYOUT FOR 6T SRAM CELL
- Publication number 20220093504
- Publication date Mar 24, 2022
- ADVANCED MICRO DEVICES, INC.
- Richard T. Schultz
- G11 - INFORMATION STORAGE
Information Patent Application
ARRANGEMENT AND THERMAL MANAGEMENT OF 3D STACKED DIES
- Publication number 20220059425
- Publication date Feb 24, 2022
- ADVANCED MICRO DEVICES, INC.
- John Wuu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SCHEME FOR ENABLING DIE REUSE IN 3D STACKED PRODUCTS
- Publication number 20210098441
- Publication date Apr 1, 2021
- ADVANCED MICRO DEVICES, INC.
- John J. Wuu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY WITH EXPANDABLE ROW WIDTH
- Publication number 20210043250
- Publication date Feb 11, 2021
- ADVANCED MICRO DEVICES, INC.
- John WUU
- G11 - INFORMATION STORAGE
Information Patent Application
TIMER FOR USE DUAL VOLTAGE SUPPLIES
- Publication number 20200312389
- Publication date Oct 1, 2020
- ADVANCED MICRO DEVICES, INC.
- Srinivas R. Sathu
- G11 - INFORMATION STORAGE
Information Patent Application
ARRANGEMENT AND THERMAL MANAGEMENT OF 3D STACKED DIES
- Publication number 20190393123
- Publication date Dec 26, 2019
- ADVANCED MICRO DEVICES, INC.
- John Wuu
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

ECC optimization

SRAM power savings and write assist

Through-silicon via layout for multi-die integrated circuits

Dual read port latch array bitcell

Single event upset tolerant memory device

Split read port latch array bit cell

Stacked die circuit routing system and method

Low power cache

Scheme for enabling die reuse in 3D stacked products

Latch bit cells

Dual-track bitline scheme for 6T SRAM cells

Memory with expandable row width

Write masked latch bit cell

Hybrid library latch array

Folded cell layout for 6T SRAM cell

In memory logic functions using memory arrays

Memory with expandable row width

Arrangement and thermal management of 3D stacked dies

Arrangement and thermal management of 3D stacked dies

Timer for use dual voltage supplies

Memory with expandable row width

Flexibile interfaces using through-silicon via technology

Configuration of multi-die modules with through-silicon vias

Arrangement and thermal management of 3D stacked dies

Programmable write word line boost for low voltage memory operation

Memory including side-car arrays with irregular sized entries

Swizzling in 3D stacked memory

VSS bitcell sleep scheme involving modified bitcell for terminating...

Pseudo-dynamic circuit for multi-voltage timing interlocks

Sidecar SRAM for high granularity in floor plan aspect ratio

Patents Applicationslast 30 patents

ECC OPTIMIZATION

DIE PAIR DEVICE PARTITIONING

ADVANCED PROCESS IN PROCESS PAIR WITHOUT FUSES

TEMPERATURE SENSORS IN DIE PAIR TOPOLOGY

BACKSIDE POWER

THERMALLY AWARE STACKING TOPOLOGY

BACK END OF LINE OPTIMIZED TO FUNCTION IN A 3D STACK CONFIGURATION

SINGLE EVENT UPSET TOLERANT MEMORY DEVICE

BACKSIDE POWER DELIVERY AND POWER GRID PATTERN TO SUPPORT 3D DIE ST...

SCHEME FOR ENABLING DIE REUSE IN 3D STACKED PRODUCTS

STACKING SEMICONDUCTOR DEVICES BY BONDING FRONT SURFACES OF DIFFERE...

THROUGH-SILICON VIA LAYOUT FOR MULTI-DIE INTEGRATED CIRCUITS

LOW POWER CACHE

DYNAMIC SETUP AND HOLD TIMES ADJUSTMENT FOR MEMORIES

SRAM POWER SAVINGS AND WRITE ASSIST

MULTI-DIE COMMUNICATIONS COUPLINGS USING A SINGLE BRIDGE DIE

DUAL READ PORT LATCH ARRAY BITCELL

SPLIT READ PORT LATCH ARRAY BIT CELL

HYBRID LIBRARY LATCH ARRAY

WRITE MASKED LATCH BIT CELL

LATCH BIT CELLS

STACKED DIE CIRCUIT ROUTING SYSTEM AND METHOD

MEMORY WITH EXPANDABLE ROW WIDTH

DUAL-TRACK BITLINE SCHEME FOR 6T SRAM CELLS

FOLDED CELL LAYOUT FOR 6T SRAM CELL

ARRANGEMENT AND THERMAL MANAGEMENT OF 3D STACKED DIES

SCHEME FOR ENABLING DIE REUSE IN 3D STACKED PRODUCTS

MEMORY WITH EXPANDABLE ROW WIDTH

TIMER FOR USE DUAL VOLTAGE SUPPLIES

ARRANGEMENT AND THERMAL MANAGEMENT OF 3D STACKED DIES