BACKGROUND
Chiplet partitioning of complex systems on chip (SoCs) has been a recently adopted feature of semiconductor products. This feature is intended to mitigate the burgeoning cost of manufacturing. Typically, such a product places the most performance hungry element (i.e., the compute chip) in the chiplet stack closest to the input/output (IO) die (e.g., interposer) to address power delivery and latency and enable flexibility of design reuse among stacked and non-stacked semiconductor devices.
BRIEF DESCRIPTION OF THE DRAWINGS AND APPENDICES
The accompanying drawings illustrate a number of exemplary implementations and are a part of the specification. Together with the following description, these drawings demonstrate and explain various principles of the present disclosure.
FIG. 1 is a flow diagram illustrating an example method for circuit die stacking.
FIG. 2 is a block diagram illustrating an example integrated circuit including an advanced node and a pair node with face to face hybrid bonded metal stacks.
FIG. 3 is a block diagram illustrating an example integrated circuit including an advanced node and a pair node with face to face hybrid bonded metal stacks and one or more temperature sensors located in the pair node.
FIG. 4 is a block diagram illustrating an example integrated circuit including an advanced node and a pair node with face to face hybrid bonded metal stacks and one or more fuses and/or phase locked loop circuits located in the pair node.
FIG. 5 is a block diagram illustrating wafer on wafer and chip on wafer processes.
FIG. 6 is a block diagram illustrating chip on wafer processes that avoid placing fuses on advanced die optimized for logic.
FIG. 7 is a block diagram illustrating an example integrated circuit including an advanced node and a pair node with hybrid bonded metal stacks and connection elements provided to the pair node.
FIG. 8 is a block diagram illustrating an example integrated circuit including a first circuit die and a second circuit die with combined metal stacks having shared metal layers.
FIG. 9 is a block diagram illustrating an example semiconductor device.
FIG. 10 is a block diagram illustrating an example semiconductor device and thermal solution.
FIG. 11 is a block diagram illustrating an example semiconductor device that demonstrates a power delivery option.
FIG. 12 is a block diagram illustrating an example semiconductor device that demonstrates a power delivery option.
FIG. 13 is a block diagram illustrating an example semiconductor device that demonstrates a power delivery option.
FIG. 14 is a block diagram illustrating bottom die that show details of power curtains with through silicon vias and backside power delivery networks.
FIG. 15 is a block diagram illustrating semiconductor devices that include power curtains with through silicon vias that require keep out zones.
FIG. 16 is a block diagram illustrating semiconductor devices that include backside power delivery networks with hybrid bonding either face to face or face to back.
FIG. 17 is a block diagram illustrating semiconductor devices that include backside power delivery networks with hybrid bonding face to back.
FIG. 18 is a block diagram illustrating an example semiconductor device that includes two die stacking with backside power delivery networks for both top and bottom die.
FIG. 19 is a block diagram illustrating an example semiconductor device that includes two die stacking with a backside power delivery network for a bottom die.
FIG. 20 is a block diagram illustrating an example semiconductor device that includes two die stacking with a backside power delivery network for a top die and backside power delivery for a bottom die having an extremely thin body and direct bonding to a package.
FIG. 21 is a block diagram illustrating an example semiconductor device that includes three die stacking with backside power delivery networks for both top and middle die.
FIG. 22 is a block diagram illustrating an example semiconductor device that includes three die stacking with a backside power delivery network for a middle die.
FIG. 23 is a block diagram illustrating an example semiconductor device that includes three die stacking with backside power delivery for a middle die having an extremely thin body and direct bonding to a bottom die.
FIG. 24 is a block diagram illustrating an example semiconductor device that includes three die stacking with backside power delivery networks for top, middle, and bottom die.
FIG. 25 is a block diagram illustrating an example semiconductor device that includes three die stacking with backside power delivery for both middle and bottom die having extremely thin body and a backside power delivery network for a top die.
Throughout the drawings, identical reference characters and descriptions indicate similar, but not necessarily identical, elements. While the exemplary implementations described herein are susceptible to various modifications and alternative forms, specific implementations have been shown by way of example in the drawings and will be described in detail herein. However, the exemplary implementations described herein are not intended to be limited to the particular forms disclosed. Rather, the present disclosure covers all modifications, equivalents, and alternatives falling within the scope of the appended claims.
DETAILED DESCRIPTION
The present disclosure is generally directed to integrated circuits and/or semiconductor devices that implement a thermally aware stacking topology. The standard way of improving thermal issues for high performance compute (HPC) die in the industry is to make larger die, which spread out the thermals over more area, thus reducing thermal density. However, by placing the compute chip (e.g., core compute die) further away from the input/output (IO) die and closer to the package thermal interface material (TIM) and thermal solution (e.g., heat sink), benefits in heat dissipation for the compute chip can be achieved. To accomplish this arrangement, a die pair device partitioning approach can be used that entails pairing of two sets of devices manufactured as separate process nodes but connected with 3D hybrid bonding (e.g., face to face). Neither of these paired nodes contain the full set of optimized devices required for a new process node, but they do so as a pair. This approach enables an “advanced” version of the process pair to include (e.g., principally or exclusively) logic transistors that are manufactured in isolation and optimized purely to improve the performance and power efficiency of logic without the compromises needed to support SRAM and analog devices. The SRAM and analog devices, plus less optimized logic devices, can be implemented (e.g., principally or exclusively) in a “pair” technology node that is also manufactured in isolation and then 3D bonded to the advanced node. The combination of the advanced and pair node in a 3D hybrid bonded configuration can deliver a much higher performing, more efficient (e.g., for logic which is the most important contributor to technology node gains), and fully functional (e.g., SRAM and analog) technology node for a SoC design. By connecting the pair node to the IO die (e.g., interposer), the advanced technology process node can be positioned away from the IO die.
Benefits obtained from the above results can include reduced thermal limiting of HPC. To keep within a cost envelope, thermal platform solutions can often fail to remove all the heat in a package. In the worst case, this failure can result in thermal runaway, which drives the product to a limited supply voltage and hence a limited performance. The situation becomes exacerbated in a 3D chiplet stacked approach in which the bottom die is challenged from a thermal dissipation perspective, especially if it is the primary thermal source in the package. Placing this chip (i.e., primary thermal source) on top of the stack away from the IO die provides a lower thermal resistance path to the hottest chip, thus ensuring cooling and mitigating associated performance losses. Accordingly, the disclosed thermally aware stacking topology can take advantage of a more efficient vertical (e.g., versus lateral) heat transfer that can keep the overall cost of the product lower compared to increasing the area of the central processing unit (CPU) die to manage thermal density.
Features from any of the implementations described herein can be used in combination with one another in accordance with the general principles described herein. These and other implementations, features, and advantages will be more fully understood upon reading the following detailed description in conjunction with the accompanying drawings and claims.
In one example, an integrated circuit includes a first circuit die having a first metal stack, wherein the first circuit die corresponds to a primary thermal source of the integrated circuit, a second circuit die having a second metal stack that is connected to the first metal stack of the first circuit die, and one or more connection elements provided to the second circuit die, wherein the one or more connection elements configure the second circuit die for connection to at least one of a package substrate or an additional die.
Another example can be the previously described example integrated circuit, wherein the first circuit die includes logic transistors that are manufactured in isolation and contains a majority of all logic transistors of the integrated circuit, and the second circuit die contains a majority of static random access memory and analog devices of the integrated circuit.
Another example can be any of the previously described example integrated circuits, wherein the second circuit die corresponds to a pair node and the first circuit die corresponds to an advanced node constructed according to a more advanced technology process compared to the pair node.
Another example can be any of the previously described example integrated circuits, wherein the one or more connection elements include one or more routing layers in the second circuit die configured for connection to the additional die using microbumps.
Another example can be any of the previously described example integrated circuits, wherein the one or more connection elements include one or more routing layers in the second circuit die configured for connection to the additional die using through silicon vias.
Another example can be any of the previously described example integrated circuits, wherein the one or more connection elements include one or more routing layers in the second circuit die configured for connection to the additional die using nano through silicon vias.
Another example can be any of the previously described example integrated circuits, wherein the one or more connection elements include one or more routing layers in the second circuit die configured for connection to the additional die using direct bonding.
Another example can be any of the previously described example integrated circuits, wherein the configuration of the second circuit die for connection configures the first circuit die for positioning closer than the second circuit die to a cooling solution of a semiconductor device containing the integrated circuit.
In one example, a semiconductor device includes an integrated circuit that includes a first circuit die connected to a second circuit die, wherein the first circuit die corresponds to a primary thermal source of the integrated circuit, an additional die, and one or more connection elements connecting the second circuit die to the additional die.
Another example can be the previously described example semiconductor device, further including a heat spreader positioned above the first circuit die.
Another example can be any of the previously described example semiconductor devices, further including thermal interface material positioned between the first circuit die and the heat spreader.
Another example can be any of the previously described example semiconductor devices, wherein the first circuit die includes logic transistors that are manufactured in isolation and contains a majority of all logic transistors of the integrated circuit, the second circuit die contains a majority of static random access memory and analog devices of the integrated circuit, and the first circuit die is constructed according to a more advanced technology process compared to the second circuit die.
Another example can be any of the previously described example semiconductor devices, wherein the one or more connection elements include one or more routing layers in the second circuit die connected to the additional die using microbumps.
Another example can be any of the previously described example semiconductor devices, wherein the one or more connection elements include one or more routing layers in the second circuit die connected to the additional die using through silicon vias.
Another example can be any of the previously described example semiconductor devices, wherein the one or more connection elements include one or more routing layers in the second circuit die connected to the additional die using nano through silicon vias.
Another example can be any of the previously described example semiconductor devices, wherein the one or more connection elements include one or more routing layers in the second circuit die connected to the additional die using direct bonding.
In one example, a method includes providing a first circuit die having a first metal stack, wherein the first circuit die corresponds to a primary thermal source of an integrated circuit including the first circuit die, providing a second circuit die of the integrated circuit, wherein the second circuit die has a second metal stack and is configured for connection to at least one of a package substrate or an additional die, and connecting the first metal stack to the second metal stack.
Another example can be the previously described example method, wherein the second circuit die has one or more routing layers therein that are configured for connection to the additional die using microbumps.
Another example can be any of the previously described example methods, wherein the second circuit die has one or more routing layers therein that are configured for connection to the additional die using through silicon vias.
Another example can be any of the previously described example methods, wherein the second circuit die has one or more routing layers therein that are configured for connection to the additional die using direct bonding.
The following will provide, with reference to FIG. 1, detailed descriptions of example methods for circuit die stacking. Detailed descriptions of corresponding integrated circuits will also be provided in connection with FIGS. 2-4, 7, and 8. In addition, detailed descriptions of example wafer on wafer and chip on wafer processes will be provided in connection with FIGS. 5 and 6. Further, detailed descriptions of example semiconductor devices will be provided in connection with FIGS. 9-25.
FIG. 1 illustrates an example method 100 for circuit die stacking. The steps shown in FIG. 1 can be performed by any suitable computer-executable code and/or computing system. In one example, each of the steps shown in FIG. 1 can represent an algorithm whose structure includes and/or is represented by multiple sub-steps, examples of which will be provided in greater detail below.
As illustrated in FIG. 1, step 102 can include providing a circuit die. For example, step 102 can include providing a first circuit die having a first metal stack, wherein the first circuit die corresponds to a primary thermal source of an integrated circuit including the first circuit die.
The term “circuit die,” as used herein, can generally refer to a small block of semiconducting material on which a given functional circuit is fabricated. For example, and without limitation, integrated circuits can be produced in large batches on a single wafer of electronic-grade silicon (EGS) or other semiconductor (e.g., GaAs) through processes such as photolithography. A wafer is cut (e.g., diced) into many pieces, each containing one copy of the circuit. Each of these pieces can be called a die. There are three commonly used plural forms: dice, die and die. To simplify handling and integration onto a printed circuit board, most die are packaged in various forms.
The term “metal stack,” as used herein, can generally refer to one or more layers of metal provided in or one a circuit die. For example, and without limitation, a metal stack can be configured as a back end of line (BEOL), a redistribution layer, wires, or any other configuration that communicatively couples transistors and/or other devices in a circuit die to one another and/or to transistors and/or other devices in another circuit die.
Step 102 can be performed in various ways. For example, the first circuit die provided in step 102 can include logic transistors that are manufactured in isolation and configured to improve performance and power efficiency of logic with reduced compromises needed to support at least one of one or more devices or one or more feature sets that would compromise performance of the logic transistors. Alternatively or additionally, the first circuit die provided in step 102 can corresponds to an advanced node constructed according to an advanced technology process facilitating improved logic functionality and performance compared to a less advanced technology process. Additional details relating to sub steps that can be performed in step 102 are provided later with reference to FIGS. 2-25.
Step 104 can include providing one or more additional circuit dies. For example, step 104 can include providing a second circuit die of the integrated circuit, wherein the second circuit die has a second metal stack and is configured for connection to at least one of a package substrate or another additional die.
The term “package substrate,” as used herein, can generally refer to a structure that transmits electrical signals between semiconductors and a main board of a computing device. For example, and without limitation, package substrates can include redistribution layers that communicatively couple to connection elements of a semiconductor device. Package substrates can also be implemented to protect semiconductors from external stress.
The term “additional die,” can generally refer to any die of semiconducting material having redistribution layers and/or circuitry of an integrated circuit. For example, and without limitation, an additional die can be an active interposer die, a circuit die of an additional integrated circuit, another die of another process-pair node, etc.
The term “active interposer die,” as used herein, can generally refer to a bottom circuit die in a stacked circuit die configuration. For example, and without limitation, an active interposer die can be used to integrate flexible and distributed interconnect fabrics for scalable chiplet traffic, energy-efficient 3D-plugs using fine pitch interconnects, power management features for power supply closer to the cores, and memory-IO controller and PHY for off-chip communication.
Step 104 can be performed in various ways. For example, the second circuit die provided in step 104 can correspond to a pair node and the first circuit die provided in step 102 can correspond to an advanced node constructed according to a more advanced technology process facilitating improved logic functionality and performance compared to the pair node. In other examples, the second circuit die provided in step 104 can have one or more routing layers therein that are configured for connection to the additional die using microbumps. Alternatively or additionally, the second circuit die provided in step 104 can have one or more routing layers therein that are configured for connection to the additional die using through silicon vias (e.g., hybrid bonds). Alternatively or additionally, the second circuit die provided in step 104 can have one or more routing layers therein that are configured for connection to the additional die using nano through silicon vias. Alternatively or additionally, the second circuit die provided in step 104 can have one or more routing layers therein that are configured for connection to the additional die using direct bonding. Additional details relating to sub steps that can be performed in step 104 are provided later with reference to FIGS. 2-25.
Step 106 can include connecting two or more metal stacks. For example, step 106 can include connecting the first metal stack to the second metal stack.
The term “connecting,” as used herein, can generally refer to physical and/or communicative coupling. For example, and without limitation, connecting can be performed using bumps, micro bumps, vias, through silicon vias (TSVs), nano through silicon vias (nTSVS), direct bonding, hybrid bonding, etc. In this context, direct bonding (e.g., silicon fusion bonding) can involve bonding of semiconductor wafers without any intervening layers (e.g., oxide layers). Direct bonding can involve wafer preprocessing (e.g., smoothing and/or polishing surfaces (e.g., silicon, metal, etc.)), prebonding (e.g., placing the polished surfaces in contact with one another) at room temperatures, and annealing at elevated temperatures to form chemical bonds. Metal layers can be directly bonded to one another by applying heat and/or pressure, for example.
Step 106 can be performed in various ways. For example, step 106 can include connecting to the first metal stack to the second metal stack face to face or back to back. Alternatively or additionally, step 106 can include connecting the first metal stack to the second metal stack using hybrid bonds, bumps, micro bumps, vias, through silicon vias, nano through silicon vias, and/or direct bonding. Additional details relating to sub steps that can be performed in step 104 are provided later with reference to FIGS. 2-25.
FIG. 2 illustrates an example integrated circuit 200 that can result from performance of method 100 of FIG. 1. Future semiconductor products will require chiplet integration of multiple die to form the final product. Two die can be connected by their respective metal stacks (e.g., flipping one die on top of the other like a sandwich). This connection can be performed using face to face stacking by hybrid bonding 210 or face to back stacking by hybrid bonding. This 3D hybrid bonding 210 can enable fine grained connectivity between the two nodes, with each node specializing in delivering optimized logic (e.g., advanced node 212), or SRAM and analog devices (e.g., pair node 214). For example, the first circuit die 202 (e.g., an advanced technology process node 212) having a first metal stack 206 and a second circuit die 204 (e.g., a pair node 214 that can be an older technology process node) having a second metal stack 208 can be connected to the first metal stack 206 of the first circuit die 202 (e.g., by face to face or face to back hybrid bonding 210).
Referring to FIG. 3, an example integrated circuit 300 can have the features described above with reference to integrated circuit 200 of FIG. 2. For example, integrated circuit 300 can include first circuit die 202 (e.g., an advanced technology process node 212) having first metal stack 206 and second circuit die 204 (e.g., a pair node 214 that can be an older technology process node) having a second metal stack 208 connected to the first metal stack 206 of the first circuit die 202 (e.g., by face to face or face to back hybrid bonding 210). Additionally, optimizing the advanced node for logic devices can involve moving some non-logic devices to the pair node 214. For example, electronic design automation (EDA) modeling can be used to predict a hot spot 302 in a transistor layer of the advanced technology process node 212 (e.g., core compute die (CCD)) and a corresponding hot spot location in the pair node 214. A temperature sensor 304 can be positioned in a transistor layer of the pair node 214 in planar proximity (e.g., directly below) the hot spot 302 in the transistor layer of the advanced technology process node 212. With this placement, spacing out the logic transistors in the advanced technology process node 212 can be avoided without placing the temperature sensor 304 far from the hot spot. In alternative implementations, the advanced technology process node 212 can be located below the pair node 214, in which case the position of the hot spot 302 can be in the bottom die and the temperature sensor 304 can be placed in the top die (e.g., directly above the hot spot 302). However, locating the advanced technology process node 212 above the pair node 214 can yield heat dissipation benefits for the advanced technology process node 212 as later detailed herein with reference to FIG. 7.
Referring to FIG. 4, an example integrated circuit 400 can have the features described above with reference to integrated circuit 200 of FIG. 2 and/or integrated circuit 300 of FIG. 3. For example, integrated circuit 400 can include first circuit die 202 (e.g., an advanced technology process node 212) having first metal stack 206 and second circuit die 204 (e.g., a pair node 214 that can be an older technology process node) having a second metal stack 208 connected to the first metal stack 206 of the first circuit die 202 (e.g., by face to face or face to back hybrid bonding 210). Additionally, optimizing the advanced node 212 for logic devices can involve moving some non-logic devices to the pair node 214. As described herein, fuses 402 normally placed in a transistor layer of a die to identify the die can be moved from the advanced node 212 to the pair node 214. Die-to-die fuse value distribution paths can be provisioned to the advanced process die of advanced node 212 so that die identification for the advanced process die can be derived from its coordinates in a wafer rather than through programmed fuses. Additionally or alternatively, one or more phase lock loop circuits can be moved from the advanced node 212 to the pair node 214 in a similar manner. Such phase lock loop circuits can be useful for clock signal generation during high speed, standalone testing.
Referring to FIG. 5, a wafer on wafer process 500A and a chip on wafer process 500B can be used to produce a die pair device such as the devices described herein with reference to FIGS. 2-4 and 7-25. For example, in wafer on wafer process 500A, placing fuses 402 and/or other non-logic components (e.g., phase lock loop circuits) exclusively on the pair process die can be relatively straightforward because die identification is only necessary after the wafers for the pair node 214 and advanced node 212 are bonded. As a result, the fuses 402 can be placed on the pair process die while provisioning fuse value distribution paths to the advanced process die, and similar provisioning can be performed for other non-logic components. However, in chip on wafer process 500B, placing fuses 402 and/or other non-logic components exclusively on the pair process die can be more complicated as the “chip” portion of the chip on wafer pair needs to support die identification and, for a number of reasons (e.g., thermal), the advanced process die often needs to be the top die in a 3D assembly. However, placing most or all of the fuses and/or other non-logic components in the pair process die and using the pair process die as the base wafer fails to retain the identification and tracking capability for the advanced process die that have already been diced into chips.
FIG. 6 illustrates chip on wafer processes 600A-600C that avoid placing fuses 402 and/or other non-logic components on advanced die optimized for logic. For example, at chip on wafer process 600A, the pair die of pair node 214 can have the fuses 402 and/or other non-logic components placed thereon and already be diced into chips for placement on the advanced process die of advanced node 212 that can be used as the base wafer. Then, one or more interface metal layers 502 can be added atop the pair die and bumped 504 in chip on wafer process 600B. Thereafter, the resulting assembly can be flipped over and diced at chip on wafer process 600C so that the advanced process die becomes the top die.
Referring to FIG. 7, an example integrated circuit 700 can have the features described above with reference to integrated circuit 200 of FIG. 2, integrated circuit 300 of FIG. 3, and/or integrated circuit 400 of FIG. 4. For example, integrated circuit 400 can include first circuit die 202 (e.g., an advanced technology process node 212) having first metal stack 206 and second circuit die 204 (e.g., a pair node 214 that can be an older technology process node) having a second metal stack 208 connected to the first metal stack 206 of the first circuit die 202 (e.g., by face to face or face to back hybrid bonding 210). Additionally, with the node specialization described above, the first circuit die 202 can correspond to the advanced technology process node 212 that is the primary thermal source of the integrated circuit 700. Also, the second circuit die 204 can correspond to the pair node 214 that can be an older technology process node compared to the advanced technology process node 212 corresponding to the first circuit die 202. By providing connection elements 702 (e.g., backside vias, through silicon vias, direct bonding, micro bumps, one or more routing layers in the second circuit die 204 configured for connection to an active interposer die and/or package substrate, etc.) to the pair node 214, the pair node 214 can be connected to an IO die (e.g., active interposer die) and/or package substrate. In this way, the advanced technology process node 212 that is the primary thermal source of the integrated circuit 700 can be placed further away from the IO die and/or package substrate, but closer to semiconductor package thermal interface material (TIM) and thermal solution (e.g., heat spreader), thus achieving benefits in heat dissipation for the advanced technology process node 212 corresponding to the first circuit die 202.
The term “backside vias,” as used herein, can generally refer to vias that directly contact a device from a backside of the die. For example, and without limitation, backside vias can directly contact circuit elements of a transistor layer of a die without connecting to metal layers in and/or on a front side of the die.
The term “nano through silicon vias,” as used herein, can generally refer to vias formed through a silicon body (e.g., having dimensions less than one micrometer) of a die and connecting to lower level metal layers on a front side of the die. For example, and without limitation, nano through silicon vias can connect to the front side metal layers of the die without requiring keep out zones from devices (e.g., circuit elements) of the die.
Referring to FIG. 8, an example integrated circuit 800 can have the features described above with reference to integrated circuit 200 of FIG. 2, integrated circuit 300 of FIG. 3, integrated circuit 400 of FIG. 4, and/or integrated circuit 700 of FIG. 7. For example, integrated circuit 800 can include first circuit die (e.g., an advanced technology process node 212) having first metal stack 206 and second circuit die (e.g., a pair node 214 that can be an older technology process node) having a second metal stack 208 connected to the first metal stack 206 of the first circuit die (e.g., by face to face or face to back hybrid bonding). Alternatively, integrated circuit 800 can include paired die that are not partitioned in a manner that optimizes one node as an advance node 212 and the other node as a pair node 214. In any event, the first circuit die and the second circuit die can have metal stacks 206 and 208 that are connected by face to face hybrid bonding into a combined metal layer stack 802.
The face to face hybrid bonding of the metal stacks 206 and 208 of the first and second circuit die can allow metal connectivity to be shared between the first circuit die and the second circuit die. This sharing of metal connectivity further allows redundant elements (e.g., metal layers) of the combined metal layer stack 802 to be eliminated from the combined stack 802. Thus, a total number of metal layers can be reduced compared to face to back or Si-metal-Si-metal stacking. For example, normal die metal stacks have N metal layers and standard stacking of two die results in 2×N metal layers. With the disclosed shared metal layer stack 802, the metal connectivity can be shared between the two die in such a manner that one or more (e.g., most or all) redundant metal layers are eliminated, resulting in <2N metal layers. In addition, at least some of the final layers to protect the die (e.g., passivation and bump) are not needed as the top of the metal stack is now embedded within the two die rather than being exposed as with a standard single die. Thus, an implementation can be a <2×N metal stack configuration of the two die.
As shown in FIG. 8, combined metal layer stack 802 can extend between a transistor layer 804 of the advanced node 212 and a transistor layer 806 of the pair node 214. Combined metal layer stack 802 include different categories of metal layers, such as a first portion 808 of metal layers utilized exclusively by the advanced node 212, a second portion 810 of metal layers utilized exclusively by the advanced node 212, metal layers 812 utilized by both the advanced node 212 and the pair node 214, and metal layers 814 utilized exclusively by the pair node 214. A circuit die normally contains all of the metal layers that it exclusively utilizes plus one or more metal layers that it uses to communicate with other die. However, as shown in FIG. 8, combined metal layer stack 802 can eliminate one or more redundant metal layers in at least two ways. Firstly, metal layers 812 utilized by both the advanced node 212 and the pair node 214 can be eliminated from the advanced node 212 and/or moved from the advanced node 212 to the pair node 214 where they can be implemented at reduced cost. Secondly, second portion 810 of metal layers utilized exclusively by the advanced node 212 can be relocated from the advanced node 212 to the pair node 214 where they can be implemented at reduced cost. Thus, a signal can route from a transistor layer 804 the advanced node 212 into second portion 810 of metal layers utilized exclusively by the advanced node 212 and therefrom back to the advanced node 212 without communication of the signal to a transistor layer 806 of the pair node 214. Accordingly, cost can be reduced by entirely eliminating one or more redundant metal layers from the combined metal stack, by relocating one or more metal layers form the first metal stack 206 to the second metal stack 208, and/or by reduced passivation layers. Additional benefits can include improved performance, reduced power, and improved reliability.
FIG. 9 illustrates an example semiconductor device 900. For example, semiconductor device 900 can include one or more integrated circuits 902 and 904, such as integrated circuit 200 of FIG. 2, integrated circuit 300 of FIG. 3, integrated circuit 400 of FIG. 4, integrated circuit 700 of FIG. 7, and/or integrated circuit 800 of FIG. 8. The one or more integrated circuits 902 and 904 can include a first circuit die corresponding to advanced node 212 and having a first metal stack and a second circuit die corresponding to a pair node 214 and having a second metal stack that is connected to the first metal stack of the first circuit die by hybrid bonding (e.g., face to face or face to back). Also, semiconductor device 900 can include connection elements (e.g., a passivation layer connected to the second circuit die and a plurality of bumps (e.g., micro bumps) connected to the passivation layer).
As mentioned above, semiconductor device 900 can include a first circuit die that corresponds to an advanced technology process node 212A and 212B and a second circuit die that corresponds to a pair node 214A and 214B, which can be an older technology process node compared to the advanced technology process node 212. Semiconductor device 900 can leverage a 3D-optimized process-pair of these nodes to enable the advanced technology process node 212A and 212B to provide compelling performance at lower cost and cycle time. The process-pair approach can yield numerous benefits, including streamlining of advanced technology process node devices (e.g., upper tier circuit die) to optimize for logic-only. Dense SRAM, analog, and less performance-critical logic can be implemented on the pair node 214A and 214B (e.g., lower tier circuit die), which can utilize N3p or N2 technology. Another benefit of the process-pair approach can be significantly higher density for higher performance firmware, enabling more compute capability.
Integrated circuits 902 and 904 can be connected to an active interposer die (AID) 906 by the micro bumps provided to the pair nodes. In turn, the AID 906 can connect (e.g., by bumps 908) to a semiconductor device package substrate 910. Additional circuit die, such as a small outline integrated circuit (SOIC) 912 can also be included in semiconductor device 900. As also mentioned above, the process-pair approach permits positioning of temperature sensors, fuses, and/or phase locked loop circuits in transistor layers of the pair nodes 214A and 214B rather than in the transistor layers of the advanced technology process nodes 212A and 212B, yielding numerous benefits. Further, the combined metal stacks of the process pair can have one or more redundant metal layers eliminated, yielding numerous benefits.
FIG. 10 illustrates an example semiconductor device 1000 that can include any or all of the features of semiconductor device 900 of FIG. 9, such as advanced node 212A and 212B, pair node 214A and 214B, integrated circuits 902 and 904, AID 906, bumps 908, package substrate 910, and/or SOIC 912. Additionally, semiconductor device 1000 can include a heat spreader 1002 located above the advanced technology process node and thermal interface material (TIM) 1004 positioned between the heat spreader 1002 and the advanced technology process node 212A and 212B. Accordingly, the advanced technology process node 212A and 212B that is the primary thermal source of the integrated circuits 902 and 904 can be placed further away from the IO die, such as AID 906 and/or package substrate 910, but closer to semiconductor package thermal interface material (TIM) 1004 and thermal solution (e.g., heat spreader 1004), thus achieving benefits in heat dissipation for the advanced technology process node 212A and 212B corresponding to the first circuit die.
FIGS. 11-13 illustrate example semiconductor devices 1100, 1200, and 1300 that demonstrate various power delivery options. Referring to FIG. 11, semiconductor device 1100 can include at least one copper redistribution layer (RDL) 1102 and a power curtain 1104 configured to convey power from connection elements 1106 and a passivation layer 1108 through a transistor layer 1110 of the second circuit die (e.g., pair node 214) to the second metal stack 208. Thus, an option for power delivery can include use of a redistribution layer 1102 and a power curtain 1104 that can correspond to one or more through silicon vias.
Referring to FIG. 12, semiconductor device 1200 can include a backside power delivery network 1202 (e.g., backside power rails) located in a passivation layer 1204 beneath a transistor layer 1206 of the second circuit die (e.g., pair node). With this configuration, the backside power delivery network 1202 can receive power through connection elements 1208 and supply power to a transistor layer 1206 of the second circuit die by backside vias and/or nano through silicon vias, and a power curtain 1210 can be eliminated. Thus, an option for power delivery can be to use a backside power delivery network 1202 located in a bottom tier of the semiconductor device 1200.
Referring to FIG. 13, semiconductor device 1300 can include a backside power delivery network 1202 (e.g., backside power rails) located in a passivation layer 1204 beneath a transistor layer 1206 of the second circuit die (e.g., pair node) and receive power from connection elements 1208 as described above with reference to semiconductor device 1200. Additionally, semiconductor device 1300 can include a top carrier 1302 and an additional passivation layer 1304 located between the first circuit die (e.g., advanced node) and the top carrier 1302. Also, semiconductor device 1300 can include an additional backside power delivery network 1306 located in the additional passivation layer 1304. With this configuration, the backside power delivery networks 1202 and 1306 can supply power to transistor layers 1204 and 1308 of the first circuit die and the second circuit die by backside vias and/or nano through silicon vias, and the power curtain 1210 can be eliminated. Thus, an option for power delivery can be to use backside power delivery networks 1202 and 1306 located in top and bottom tiers of the semiconductor device 1300.
Referring to FIG. 14, bottom die 1400A and 1400B are shown in greater detail. For example, bottom die 1400A shows a bottom die that does not have backside power, and that requires one or more power curtains (e.g., TSVs) 1402A and 1402B through the transistor layer (e.g., circuit 1404) to a landing metal 1406 in a metal stack on a front side of the die. These power curtains 1402A and 1402B require keep out zones 1406A and 1406B that space the power curtains 1402A and 1402B apart from active elements 1408 of the transistor layer, thus increasing a size of the bottom die 1400A to prevent device degradation and resulting in higher cost. Also, delivering power to the circuit 1404 from the landing metal 1406 through the power strapping 1410 (e.g., metal stacks) on the front side of the die 1400A requires additional connection and potential performance impact with additional IR drop.
In contrast to bottom die 1400A, bottom die 1400B has a backside power delivery network 1450 that directly receives power from connection elements 1452 and delivers power to the transistor layer 1454 from an active interposer die or package substrate through micro bumps and backside vias or nano TSVs 1456 that do not require keep out zones. As a result, a size of the bottom die 1400B can be reduced and delivery of power to the circuit from a landing metal through power strapping (e.g., metal stacks) on the front side of the die 1400B can be avoided. Thus, the backside power delivery network 1450 can provide power directly to the transistor layer 1454 of the bottom die 1400B while avoiding higher costs, potential performance impact, and additional IR drop that results from use of power curtains that require keep out zones and deliver power first to the front side of a bottom die. The power provided directly to the transistor layer 1454 of the bottom die 1400B can also pass through the bottom die 1400B and provide power to a top die through the front side of the bottom die 1400B by power and signal connections 1458 to the top die. Alternatively or additionally, a same or similar backside power delivery network 1450 can be provided to the top die, thus avoiding potential IR drop resulting from delivering power to the circuit (e.g., transistor layer) of the top die through power strapping (e.g., metal stacks) on the front side of the top die.
Referring to FIG. 15, semiconductor devices 1500A and 1500B can include top and bottom die that are hybrid bonded 1502A and 1502B and stacked face to back and face to face, respectively. Without backside power, both of semiconductor devices 1500A and 1500B utilize power curtains 1504A and 1504B (e.g., arrays of TSVs) that supply power to the top and bottom die.
Referring to FIG. 16, semiconductor devices 1600A, 1600B, and 1600C can include top and bottom die that have metal stacks that are hybrid bonded to one another. For example, semiconductor devices 1600A and 1600B can be hybrid bonded face to face and semiconductor device 1600C can be hybrid bonded face to back with a face of the top die bonded to a back of the bottom die. Semiconductor devices 1600A, 1600B, and 1600C can implement the backside power delivery networks described above with reference to FIGS. 12-14. For example, semiconductor device 1600A can have a backside power delivery network 1602 located in a passivation layer of the bottom die 1604. This backside power delivery network 1602 can be configured to deliver power from an active interposer die and/or package substrate 1606 to both the top die 1608 and bottom die 1604 that have metal stacks that are face to face hybrid bonded to one another. Additionally, semiconductor device 1600B can have backside power delivery networks 1630 and 1632 located in passivation layers of the top die 1634 and bottom die 1636. The backside power delivery networks 1630 and 1632 can be configured to deliver power from an active interposer die and/or package substrate 1638 to the bottom die 1636 and from a top carrier 1640 to the top die 1634. Also, semiconductor device 1600C can have a backside power delivery network 1660 located in a passivation layer of the bottom die 1662. This backside power delivery network 1660 can be configured to deliver power from an active interposer die and/or package substrate 1664 to both the top die 1666 and bottom die 1662 that have metal stacks that are face to face hybrid bonded to one another. With any of these arrangements, semiconductor devices 1600A, 1600B, and 1600C can deliver power to their respective top and bottom die without use of arrays of through silicon vias (TSVs) (e.g., power curtains) through the circuits (e.g., transistor layers) of the bottom die.
Referring to FIG. 17, semiconductor devices 1700A, 1700B, and 1700C can include top and bottom die that have metal stacks that are hybrid bonded to one another face to back. For example, semiconductor device 1700A can bond the face of the top die 1702 to the back of the bottom die 1704. Additionally, semiconductor device 1700B can bond the face of the bottom die 1732 to the back of the top die 1734. Also, semiconductor device 1700C can bond the face of the bottom die 1762 to the back of the top die 1764.
Semiconductor devices 1700A, 1700B, and 1700C can implement the backside power delivery networks described above with reference to FIGS. 12-14. For example, semiconductor device 1700A can have backside power delivery networks 1706 and 1708 located in passivation layers of the top die 1702 and bottom die 1704. The backside power delivery networks 1706 and 1708 can be configured to deliver power from an active interposer die and/or package substrate 1710 to the bottom die 1704 and from a top carrier 1712 to the top die 1702. Additionally, semiconductor device 1700B can have a backside power delivery network 1736 located in a passivation layer of the bottom die 1732. This backside power delivery network 1736 can be configured to deliver power from an active interposer die and/or package substrate 1738 to both the top die 1734 and bottom die 1732 using power curtains 1740. Also, semiconductor device 1700C can have backside power delivery networks 1766 and 1768 located in passivation layers of the top die 1764 and bottom die 1762. The backside power delivery networks 1766 and 1768 can be configured to deliver power from an active interposer die and/or package substrate 1770 to the bottom die 1762 and to the top die 1764.
Referring to FIG. 18, an example semiconductor device 1800 can include two die stacking with a backside power delivery networks 1802 and 1804 for both top and bottom die 1806 and 1808, respectively. Power delivery network 1804 can receive power from connection elements 1810 and supply power to the bottom die 1808 using one or more backside vias 1812 and/or one or more nano through silicon vias 1814 and a power plane 1816. Frontside metal layers can also direct power through one or more hybrid bonds 1818 to a power curtain 1820 of top die 1806. A nano through silicon via 1822 can feed this power to backside power delivery network 1802 and one or more backside vias 1824 to circuit elements of the top die 1806. Semiconductor device 1800 can also have a signal feed through 1826 by one or more nano through silicon vias 1828.
Referring to FIG. 19, an example semiconductor device 1900 can include two die stacking with backside power delivery network 1902 for a bottom die 1904. Backside power delivery network 1902 can receive power from connection elements 1906 and supply power to the bottom die 1904 using one or more backside vias 1908 and/or one or more nano through silicon vias 1910 and a power plane 1912. Frontside metal layers can also direct power through one or more hybrid bonds 1914 to a frontside power delivery network 1916 of top die 1918. Frontside power delivery network 1916 can feed power to circuit elements of the top die 1918. Semiconductor device 1900 can also have a signal feed through 1920 by one or more nano through silicon vias 1922.
Referring to FIG. 20, an example semiconductor device 2000 can include two die stacking with a backside power delivery network 2002 for a top die 2004 and backside power delivery for a bottom die 2006 having an extremely thin body and direct bonding to a package. Bottom die 2006 can receive power from connection elements 2008 (e.g., direct bonding) and supply power to the bottom die 2006 using one or more nano through silicon vias 2010 and one or more power curtains 2012 and/or a power plane 2014. Frontside metal layers can also direct power through one or more hybrid bonds 2016 to a power curtain 2018 of top die 2004, which can supply power to backside power delivery network 2002 using one or more nano through silicon vias 2020. Backside power delivery network 2002 can feed power to circuit elements of the top die 2004 using backside vias 2022. Semiconductor device 2000 can also have a signal feed through 2024 by one or more nano through silicon vias 2026.
Referring to FIG. 21, an example semiconductor device 2100 includes three die stacking with backside power delivery networks 2102 and 2104 for both a top die 2106 and a middle die 2108, respectively. A bottom die 2110 can correspond to an active interposer die. Connection elements 2112 of bottom die 2110 can receive power from a package substrate and convey the power by power curtains 2114 to a metal landing layer 2116 of a frontside power delivery network 2118 of the bottom die 2110. Frontside power delivery network 2118 can provide power to bottom die circuitry and also provide power to backside power delivery network 2104 using hybrid bonds 2120. Backside power delivery network 2104 can supply power to the middle die 2108 using one or more backside vias 2122 and/or one or more nano through silicon vias 2124 and a power plane 2126. Frontside metal layers can also direct power through one or more hybrid bonds 2128, power curtains 2130, and nano through silicon vias 2132 to backside power delivery network 2102 of top die 2106. Backside power delivery network 2102 can feed power to circuit elements of the top die 2106 by backside vias 2134. Semiconductor device 2100 can also have a signal feed through 2136 by one or more nano through silicon vias 2138 and 2140 and hybrid bonds 2120.
Referring to FIG. 22, an example semiconductor device 2200 can include three die stacking with a backside power delivery network 2202 for a middle die 2204 and a frontside power delivery network 2206 for a top die 2208. A bottom die 2210 can correspond to an active interposer die. Connection elements 2212 of bottom die 2210 can receive power from a package substrate and convey the power by power curtains 2214 to a metal landing layer 2216 of a frontside power delivery network 2218 of the bottom die 2210. Frontside power delivery network 2218 can provide power to bottom die circuitry and also provide power to backside power delivery network 2202 using hybrid bonds 2220. Backside power delivery network 2202 can supply power to the middle die 2204 using one or more backside vias 2222 and/or one or more nano through silicon vias 2224 and a power plane 2226. Frontside metal layers can also direct power through one or more hybrid bonds 2228 to frontside power delivery network 2206 of top die 2208. Frontside power delivery network 2206 can feed power to circuit elements of the top die 2108. Semiconductor device 2100 can also have a signal feed through 2236 by one or more nano through silicon vias 2238 and 2240 and hybrid bonds 2220.
Referring to FIG. 23, an example semiconductor device 2300 can include three die stacking with backside power delivery for a middle die 2302 having an extremely thin body 2304 and direct bonding 2306 and/or hybrid bonding to a bottom die 2308 having a frontside power delivery network 2310. Bottom die 2308 can correspond to an active interposer die. Connection elements 2312 of bottom die 2308 can receive power from a package substrate and convey the power by power curtains 2314 to a metal landing layer 2316 of frontside power delivery network 2310 of the bottom die 2308. Frontside power delivery network 2310 can provide power to bottom die circuitry and also provide power to extremely thin body 2304 of middle die 2302 using direct bonding 2306 and/or hybrid bonding. The extremely thin body 2304 can supply power to the middle die 2302 using one or more one or more nano through silicon vias 2318 and 2320 and a power plane 2322. Frontside metal layers can also direct power through one or more hybrid bonds 2324, power curtains 2326, and nano through silicon vias 2328 to backside power delivery network 2330 of top die 2332. Backside power delivery network 2330 can feed power to circuit elements of the top die 2332 by backside vias 2334. Semiconductor device 2300 can also have a signal feed through 2336 by one or more nano through silicon vias 2338 and 2340 and direct bonding 2306 and/or hybrid bonding.
Referring to FIG. 24, an example semiconductor device can include three die stacking with backside power delivery networks 2402, 2404, and 2406 for a top die 2408, a middle die 2410, and a bottom die 2412. Bottom die 2412 can correspond to an active interposer die. Connection elements 2414 of bottom die 2412 can receive power from a package substrate and convey the power to backside power delivery network 2406. Backside power delivery network 2406 can supply power to the bottom die 2412 using one or more backside vias 2415 and/or one or more nano through silicon vias 2416 and a power plane 2418. Frontside metal layers can also direct power through one or more hybrid bonds 2420 to backside power delivery network 2404. Backside power delivery network 2404 can supply power to the middle die 2410 using one or more backside vias 2422 and/or one or more nano through silicon vias 2424 and a power plane 2426. Frontside metal layers can also direct power through one or more hybrid bonds 2428, power curtains 2430, and nano through silicon vias 2432 to backside power delivery network 2402 of top die 2408. Backside power delivery network 2402 can feed power to circuit elements of the top die 2408 by backside vias 2434. Semiconductor device 2400 can also have one or more signal feed throughs 2436 and 2438 by one or more nano through silicon vias 2440 and 2442 and hybrid bonds 2420.
Referring to FIG. 25, an example semiconductor device 2500 can include three die stacking with backside power delivery for both a middle die 2502 and bottom die 2504 having extremely thin body 2506 and 2508 and a backside power delivery network 2510 for a top die 2512. Bottom die 2504 can correspond to an active interposer die. Connection elements 2514 of bottom die 2504 can receive power from a package substrate and convey the power to extremely thin body 2506 of bottom die 2504. The extremely thin body 2506 can supply power to the bottom die 2504 using one or more one or more nano through silicon vias 2516 and 2518 and a power plane 2520. Frontside metal layers can also direct power through direct bonding 2521 and/or hybrid bonds to extremely thin body 2508 of the middle die 2502. The extremely thin body 2508 can supply power to the middle die 2502 using one or more nano through silicon vias 2524 and 2526 and a power plane 2528. Frontside metal layers can also direct power through one or more hybrid bonds 2530, power curtains 2532, and nano through silicon vias 2534 to backside power delivery network 2510 of top die 2512. Backside power delivery network 2510 can feed power to circuit elements of the top die 2512 by backside vias 2536. Semiconductor device 2500 can also have signal feed throughs 2538 and 2540 by one or more nano through silicon vias 2542 and 2544 and direct bonding 2521 and/or hybrid bonding.
As detailed above a thermally aware stacking topology places the compute chip (e.g., core compute die) further away from the IO die but closer to the package thermal interface material (TIM) and thermal solution (e.g., heat sink), thus achieving benefits in heat dissipation for the compute chip. By connecting the pair node to the IO die (e.g., interposer), the advanced technology process node can be positioned away from the IO die.
Benefits obtained from the above results can include reduced thermal limiting of HPC. Placing the compute chip (i.e., primary thermal source) on top of the stack away from the IO die provides a lower thermal resistance path to the hottest chip, thus ensuring cooling and mitigating associated performance losses. Accordingly, the disclosed thermally aware stacking topology can take advantage of a more efficient vertical (e.g., versus lateral) heat transfer that can keep the overall cost of the product lower compared to increasing the area of the central processing unit (CPU) die to manage thermal density.
The process parameters and sequence of the steps described and/or illustrated herein are given by way of example only and can be varied as desired. For example, while the steps illustrated and/or described herein are shown or discussed in a particular order, these steps do not necessarily need to be performed in the order illustrated or discussed. The various exemplary methods described and/or illustrated herein can also omit one or more of the steps described or illustrated herein or include additional steps in addition to those disclosed.
The preceding description has been provided to enable others skilled in the art to best utilize various aspects of the exemplary implementations disclosed herein. This exemplary description is not intended to be exhaustive or to be limited to any precise form disclosed. Many modifications and variations are possible without departing from the spirit and scope of the present disclosure. The implementations disclosed herein should be considered in all respects illustrative and not restrictive. Reference should be made to the appended claims and their equivalents in determining the scope of the present disclosure.
Unless otherwise noted, the terms “connected to” and “coupled to” (and their derivatives), as used in the specification and claims, are to be construed as permitting both direct and indirect (i.e., via other elements or components) connection. In addition, the terms “a” or “an,” as used in the specification and claims, are to be construed as meaning “at least one of.” Finally, for ease of use, the terms “including” and “having” (and their derivatives), as used in the specification and claims, are interchangeable with and have the same meaning as the word “comprising.”
Patent Application
20240321827
