Joji PHILIP

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Enhanced page locality in network-on-chip (NoC) architectures
- Patent number 11,144,457
- Issue date Oct 12, 2021
- Netspeed Systems, Inc.
- Joseph Rowlands
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bandwidth weighting mechanism based network-on-chip (NoC) configura...
- Patent number 10,983,910
- Issue date Apr 20, 2021
- Netspeed Systems, Inc.
- Joseph Rowlands
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface virtualization and fast path for Network on Chip
- Patent number 10,749,811
- Issue date Aug 18, 2020
- Netspeed Systems, Inc.
- Joseph Rowlands
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Interface virtualization and fast path for network on chip
- Patent number 10,735,335
- Issue date Aug 4, 2020
- Netspeed Systems, Inc.
- Joseph Rowlands
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Heterogeneous channel capacities in an interconnect
- Patent number 10,355,996
- Issue date Jul 16, 2019
- Sailesh Kumar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multiple clock domains in NoC
- Patent number 10,027,433
- Issue date Jul 17, 2018
- NetSpeed Systems
- Joji Philip
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dynamically configuring store-and-forward channels and cut-through...
- Patent number 9,825,809
- Issue date Nov 21, 2017
- NetSpeed Systems
- Joji Philip
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Identification of internal dependencies within system components fo...
- Patent number 9,781,043
- Issue date Oct 3, 2017
- NetSpeed Systems
- Sailesh Kumar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Hierarchical asymmetric mesh with virtual routers
- Patent number 9,774,498
- Issue date Sep 26, 2017
- NetSpeed Systems
- Sailesh Kumar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Configurable router for a network on chip (NoC)
- Patent number 9,742,630
- Issue date Aug 22, 2017
- NetSpeed Systems
- Joji Philip
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Supporting multicast in NoC interconnect
- Patent number 9,590,813
- Issue date Mar 7, 2017
- NetSpeed Systems
- Sailesh Kumar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Supporting multicast in NOC interconnect
- Patent number 9,473,388
- Issue date Oct 18, 2016
- NetSpeed Systems
- Sailesh Kumar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Hierarchical asymmetric mesh with virtual routers
- Patent number 9,253,085
- Issue date Feb 2, 2016
- NetSpeed Systems
- Sailesh Kumar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Automatic construction of deadlock free interconnects
- Patent number 9,244,880
- Issue date Jan 26, 2016
- NetSpeed Systems
- Joji Philip
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Combining associativity and cuckoo hashing
- Patent number 9,223,711
- Issue date Dec 29, 2015
- NetSpeed Systems
- Joji Philip
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tagging and synchronization for fairness in NOC interconnects
- Patent number 9,185,026
- Issue date Nov 10, 2015
- NetSpeed Systems
- Sailesh Kumar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory mapping and translation for arbitrary number of memory units
- Patent number 9,135,170
- Issue date Sep 15, 2015
- FutureWei Technologies, Inc.
- Sailesh Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Creating multiple NoC layers for isolation or avoiding NoC traffic...
- Patent number 9,130,856
- Issue date Sep 8, 2015
- NetSpeed Systems
- Sailesh Kumar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
QoS in heterogeneous NoC by assigning weights to NoC node channels...
- Patent number 9,007,920
- Issue date Apr 14, 2015
- NetSpeed Systems
- Sailesh Kumar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Automatic deadlock detection and avoidance in a system interconnect...
- Patent number 9,009,648
- Issue date Apr 14, 2015
- NetSpeed Systems
- Sailesh Kumar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Heterogeneous channel capacities in an interconnect
- Patent number 8,885,510
- Issue date Nov 11, 2014
- NetSpeed Systems
- Sailesh Kumar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Asymmetric mesh NoC topologies
- Patent number 8,819,616
- Issue date Aug 26, 2014
- NetSpeed Systems
- Joji Philip
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Asymmetric mesh NoC topologies
- Patent number 8,819,611
- Issue date Aug 26, 2014
- NetSpeed Systems
- Joji Philip
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asymmetric mesh NoC topologies
- Patent number 8,601,423
- Issue date Dec 3, 2013
- NetSpeed Systems
- Joji Philip
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
STREAMING FABRIC INTERFACE
- Publication number 20230342323
- Publication date Oct 26, 2023
- Mohannad Fahim Ali
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUILT-IN SELF-TEST FOR NETWORK ON CHIP FABRIC
- Publication number 20210373075
- Publication date Dec 2, 2021
- Intel Corporation
- Dawn Maxon
- G01 - MEASURING TESTING
Information Patent Application
ENHANCED PAGE LOCALITY IN NETWORK-ON-CHIP (NOC) ARCHITECTURES
- Publication number 20190258572
- Publication date Aug 22, 2019
- NetSpeed Systems, Inc.
- Joseph ROWLANDS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR MAINTAINING NETWORK-ON-CHIP (NOC) SAFETY AN...
- Publication number 20190260504
- Publication date Aug 22, 2019
- NetSpeed Systems, Inc.
- Joji Philip
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
BANDWIDTH WEIGHTING MECHANISM BASED NETWORK-ON-CHIP (NOC) CONFIGURA...
- Publication number 20190258573
- Publication date Aug 22, 2019
- NetSpeed Systems, Inc.
- Joseph ROWLANDS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERFACE VIRTUALIZATION AND FAST PATH FOR NETWORK ON CHIP
- Publication number 20180191626
- Publication date Jul 5, 2018
- NetSpeed Systems, Inc.
- Joseph Rowlands
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
INTERFACE VIRTUALIZATION AND FAST PATH FOR NETWORK ON CHIP
- Publication number 20180183722
- Publication date Jun 28, 2018
- NetSpeed Systems, Inc.
- Joseph Rowlands
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
INTERFACE VIRTUALIZATION AND FAST PATH FOR NETWORK ON CHIP
- Publication number 20180183721
- Publication date Jun 28, 2018
- NetSpeed Systems, Inc.
- Joseph Rowlands
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
INTERFACE VIRTUALIZATION AND FAST PATH FOR NETWORK ON CHIP
- Publication number 20180159786
- Publication date Jun 7, 2018
- NetSpeed Systems, Inc.
- Joseph Rowlands
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DYNAMICALLY CONFIGURING STORE-AND-FORWARD CHANNELS AND CUT-THROUGH...
- Publication number 20170063609
- Publication date Mar 2, 2017
- NETSPEED SYSTEMS
- Joji PHILIP
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SUPPORTING MULTICAST IN NOC INTERCONNECT
- Publication number 20170063564
- Publication date Mar 2, 2017
- NETSPEED SYSTEMS
- Sailesh KUMAR
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
HIERARCHICAL ASYMMETRIC MESH WITH VIRTUAL ROUTERS
- Publication number 20170063610
- Publication date Mar 2, 2017
- NETSPEED SYSTEMS
- Sailesh KUMAR
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CONFIGURABLE ROUTER FOR A NETWORK ON CHIP (NOC)
- Publication number 20170063625
- Publication date Mar 2, 2017
- NETSPEED SYSTEMS
- Joji PHILIP
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
HETEROGENEOUS CHANNEL CAPACITIES IN AN INTERCONNECT
- Publication number 20170063693
- Publication date Mar 2, 2017
- NETSPEED SYSTEMS
- Sailesh Kumar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
COMBINING ASSOCIATIVITY AND CUCKOO HASHING
- Publication number 20150052309
- Publication date Feb 19, 2015
- NETSPEED SYSTEMS
- Joji PHILIP
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPPORTING MULTICAST IN NOC INTERCONNECT
- Publication number 20150043575
- Publication date Feb 12, 2015
- NETSPEED SYSTEMS
- Sailesh KUMAR
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
IDENTIFICATION OF INTERNAL DEPENDENCIES WITHIN SYSTEM COMPONENTS FO...
- Publication number 20150016257
- Publication date Jan 15, 2015
- NETSPEED SYSTEMS
- Sailesh KUMAR
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MULTIPLE CLOCK DOMAINS IN NOC
- Publication number 20140376569
- Publication date Dec 25, 2014
- Joji PHILIP
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYMMETRIC MESH NOC TOPOLOGIES
- Publication number 20140331027
- Publication date Nov 6, 2014
- Joji Philip
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CREATING MULTIPLE NOC LAYERS FOR ISOLATION OR AVOIDING NOC TRAFFIC...
- Publication number 20140211622
- Publication date Jul 31, 2014
- NETSPEED SYSTEMS
- Sailesh KUMAR
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
QOS IN HETEROGENEOUS NOC BY ASSIGNING WEIGHTS TO NOC NODE CHANNELS...
- Publication number 20140204764
- Publication date Jul 24, 2014
- NETSPEED SYSTEMS
- Sailesh KUMAR
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
AUTOMATIC DEADLOCK DETECTION AND AVOIDANCE IN A SYSTEM INTERCONNECT...
- Publication number 20140204735
- Publication date Jul 24, 2014
- NETSPEED SYSTEMS
- Sailesh KUMAR
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TAGGING AND SYNCHRONIZATION FOR FAIRNESS IN NOC INTERCONNECTS
- Publication number 20140177648
- Publication date Jun 26, 2014
- NETSPEED SYSTEMS
- Sailesh KUMAR
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
HIERARCHICAL ASYMMETRIC MESH WITH VIRTUAL ROUTERS
- Publication number 20140177473
- Publication date Jun 26, 2014
- NETSPEED SYSTEMS
- Sailesh KUMAR
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
ASYMMETRIC MESH NoC TOPOLOGIES
- Publication number 20140115298
- Publication date Apr 24, 2014
- NETSPEED SYSTEMS
- Joji PHILIP
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYMMETRIC MESH NoC TOPOLOGIES
- Publication number 20140115218
- Publication date Apr 24, 2014
- NETSPEED SYSTEMS
- Joji PHILIP
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HETEROGENEOUS CHANNEL CAPACITIES IN AN INTERCONNECT
- Publication number 20140098683
- Publication date Apr 10, 2014
- NetSpeed Systems
- Sailesh KUMAR
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
AUTOMATIC CONSTRUCTION OF DEADLOCK FREE INTERCONNECTS
- Publication number 20140068132
- Publication date Mar 6, 2014
- NetSpeed Systems
- Joji PHILIP
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Mapping and Translation for Arbitrary Number of Memory Units
- Publication number 20130311747
- Publication date Nov 21, 2013
- FutureWei Technologies, Inc.
- Sailesh Kumar
- G06 - COMPUTING CALCULATING COUNTING

Joji PHILIP

Person

Patents Grantslast 30 patents

Enhanced page locality in network-on-chip (NoC) architectures

Bandwidth weighting mechanism based network-on-chip (NoC) configura...

Interface virtualization and fast path for Network on Chip

Interface virtualization and fast path for network on chip

Heterogeneous channel capacities in an interconnect

Multiple clock domains in NoC

Dynamically configuring store-and-forward channels and cut-through...

Identification of internal dependencies within system components fo...

Hierarchical asymmetric mesh with virtual routers

Configurable router for a network on chip (NoC)

Supporting multicast in NoC interconnect

Supporting multicast in NOC interconnect

Hierarchical asymmetric mesh with virtual routers

Automatic construction of deadlock free interconnects

Combining associativity and cuckoo hashing

Tagging and synchronization for fairness in NOC interconnects

Memory mapping and translation for arbitrary number of memory units

Creating multiple NoC layers for isolation or avoiding NoC traffic...

QoS in heterogeneous NoC by assigning weights to NoC node channels...

Automatic deadlock detection and avoidance in a system interconnect...

Heterogeneous channel capacities in an interconnect

Asymmetric mesh NoC topologies

Asymmetric mesh NoC topologies

Asymmetric mesh NoC topologies

Patents Applicationslast 30 patents

STREAMING FABRIC INTERFACE

BUILT-IN SELF-TEST FOR NETWORK ON CHIP FABRIC

ENHANCED PAGE LOCALITY IN NETWORK-ON-CHIP (NOC) ARCHITECTURES

SYSTEMS AND METHODS FOR MAINTAINING NETWORK-ON-CHIP (NOC) SAFETY AN...

BANDWIDTH WEIGHTING MECHANISM BASED NETWORK-ON-CHIP (NOC) CONFIGURA...

INTERFACE VIRTUALIZATION AND FAST PATH FOR NETWORK ON CHIP

INTERFACE VIRTUALIZATION AND FAST PATH FOR NETWORK ON CHIP

INTERFACE VIRTUALIZATION AND FAST PATH FOR NETWORK ON CHIP

INTERFACE VIRTUALIZATION AND FAST PATH FOR NETWORK ON CHIP

DYNAMICALLY CONFIGURING STORE-AND-FORWARD CHANNELS AND CUT-THROUGH...

SUPPORTING MULTICAST IN NOC INTERCONNECT

HIERARCHICAL ASYMMETRIC MESH WITH VIRTUAL ROUTERS

CONFIGURABLE ROUTER FOR A NETWORK ON CHIP (NOC)

HETEROGENEOUS CHANNEL CAPACITIES IN AN INTERCONNECT

COMBINING ASSOCIATIVITY AND CUCKOO HASHING

SUPPORTING MULTICAST IN NOC INTERCONNECT

IDENTIFICATION OF INTERNAL DEPENDENCIES WITHIN SYSTEM COMPONENTS FO...

MULTIPLE CLOCK DOMAINS IN NOC

ASYMMETRIC MESH NOC TOPOLOGIES

CREATING MULTIPLE NOC LAYERS FOR ISOLATION OR AVOIDING NOC TRAFFIC...

QOS IN HETEROGENEOUS NOC BY ASSIGNING WEIGHTS TO NOC NODE CHANNELS...

AUTOMATIC DEADLOCK DETECTION AND AVOIDANCE IN A SYSTEM INTERCONNECT...

TAGGING AND SYNCHRONIZATION FOR FAIRNESS IN NOC INTERCONNECTS

HIERARCHICAL ASYMMETRIC MESH WITH VIRTUAL ROUTERS

ASYMMETRIC MESH NoC TOPOLOGIES

ASYMMETRIC MESH NoC TOPOLOGIES

HETEROGENEOUS CHANNEL CAPACITIES IN AN INTERCONNECT

AUTOMATIC CONSTRUCTION OF DEADLOCK FREE INTERCONNECTS

Memory Mapping and Translation for Arbitrary Number of Memory Units