Jon A. Masamitsu

Person

Livermore, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Split-reference, two-pass mark-compaction
- Patent number 7,389,395
- Issue date Jun 17, 2008
- Sun Microsystems, Inc.
- Alexander T. Garthwaite
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for user side scheduling in a multiprocessor o...
- Patent number 6,195,676
- Issue date Feb 27, 2001
- Silicon Graphics, Inc.
- George A. Spix
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for a distributed debugger for debugging distribu...
- Patent number 6,042,614
- Issue date Mar 28, 2000
- Sun Microsystems, Inc.
- Andrew E. Davidson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for run-time memory access checking and memory...
- Patent number 5,953,530
- Issue date Sep 14, 1999
- Sun Microsystems, Inc.
- Alok Rishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for a distributed debugger for debugging distribu...
- Patent number 5,819,093
- Issue date Oct 6, 1998
- Sun Microsystems, Inc.
- Andrew E. Davidson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual level scheduling of processes to multiple parallel regions of...
- Patent number 5,339,415
- Issue date Aug 16, 1994
- Cray Research, Inc.
- Robert E. Strout
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for controlling a highly parallel multiprocessor...
- Patent number 5,179,702
- Issue date Jan 12, 1993
- SuperComputer Systems Limited Partnership
- George A. Spix
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer with integrated hierarchical representation (IHR) of progr...
- Patent number 5,175,856
- Issue date Dec 29, 1992
- SuperComputer Systems Limited Partnership
- Don A. Van Dyke
- G06 - COMPUTING CALCULATING COUNTING

Jon A. Masamitsu

Person

Patents Grantslast 30 patents

Split-reference, two-pass mark-compaction

Method and apparatus for user side scheduling in a multiprocessor o...

System and method for a distributed debugger for debugging distribu...

Method and apparatus for run-time memory access checking and memory...

System and method for a distributed debugger for debugging distribu...

Dual level scheduling of processes to multiple parallel regions of...

System and method for controlling a highly parallel multiprocessor...

Computer with integrated hierarchical representation (IHR) of progr...