Jon Allan Faue

Person

Colorado Springs, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Linear progression delay register
- Patent number 9,350,338
- Issue date May 24, 2016
- United Memories, Inc.
- Jon Allan Faue
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Linear progression delay register
- Patent number 9,252,759
- Issue date Feb 2, 2016
- United Memories, Inc.
- Jon Allan Faue
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dual-complementary integrating duty cycle detector with dead band n...
- Patent number 9,246,475
- Issue date Jan 26, 2016
- United Memories, Inc.
- Oscar Frederick Jones
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Shielding of datalines with physical placement based on time stagge...
- Patent number 8,594,114
- Issue date Nov 26, 2013
- ProMOS Technologies Pte. Ltd.
- Jon Faue
- G11 - INFORMATION STORAGE
Information Patent Grant
Using differential data strobes in non-differential mode to enhance...
- Patent number 7,889,579
- Issue date Feb 15, 2011
- ProMOS Technologies Pte. Ltd.
- Jon Allan Faue
- G11 - INFORMATION STORAGE
Information Patent Grant
Asymetric data path position and delays technique enabling high spe...
- Patent number 7,830,734
- Issue date Nov 9, 2010
- ProMOS Technologies Pte. Ltd.
- Jon Allan Faue
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-bank block architecture for integrated circuit memory devices...
- Patent number 7,764,565
- Issue date Jul 27, 2010
- ProMOS Technologies Pte. Ltd.
- Jon Allan Faue
- G11 - INFORMATION STORAGE
Information Patent Grant
Wide window clock scheme for loading output FIFO registers
- Patent number 7,440,351
- Issue date Oct 21, 2008
- ProMOS Technologies Pte. Ltd.
- Jon Allan Faue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two-bit per I/O line write data bus for DDR1 and DDR2 operating mod...
- Patent number 7,349,289
- Issue date Mar 25, 2008
- ProMos Technologies Inc.
- Jon Allan Faue
- G11 - INFORMATION STORAGE
Information Patent Grant
Tri-mode clock generator to control memory array access
- Patent number 7,298,669
- Issue date Nov 20, 2007
- ProMos Technologies, Inc.
- Jon Allan Faue
- G11 - INFORMATION STORAGE
Information Patent Grant
Efficient register for additive latency in DDR2 mode of operation
- Patent number 7,251,172
- Issue date Jul 31, 2007
- ProMos Technologies Inc.
- Jon Allan Faue
- G11 - INFORMATION STORAGE
Information Patent Grant
Tri-mode clock generator to control memory array access
- Patent number 7,224,637
- Issue date May 29, 2007
- ProMos Technologies Inc.
- Jon Allan Faue
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual equalization devices for long data line pairs
- Patent number 7,218,564
- Issue date May 15, 2007
- ProMos Technologies Inc.
- Jon Allan Faue
- G11 - INFORMATION STORAGE
Information Patent Grant
Low voltage differential amplifier circuit for wide voltage range o...
- Patent number 7,167,052
- Issue date Jan 23, 2007
- ProMos Technologies Inc.
- John D. Heightley
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low voltage differential amplifier circuit and a sampled low power...
- Patent number 7,102,439
- Issue date Sep 5, 2006
- ProMos Technologies Inc.
- John D. Heightley
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reduced device count level shifter with power savings
- Patent number 7,091,746
- Issue date Aug 15, 2006
- ProMos Technologies Inc.
- Jon Allan Faue
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Limited output address register technique providing selectively var...
- Patent number 7,061,823
- Issue date Jun 13, 2006
- ProMos Technologies Inc.
- Jon Allan Faue
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit memory architecture with selectively offset data...
- Patent number 7,039,822
- Issue date May 2, 2006
- ProMos Technologies Inc.
- Jon Allan Faue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data sorting in memories
- Patent number 7,016,235
- Issue date Mar 21, 2006
- ProMOS Technologies Pte. Ltd.
- Jon Allan Faue
- G11 - INFORMATION STORAGE
Information Patent Grant
Limited variable width internal clock generation
- Patent number 6,903,592
- Issue date Jun 7, 2005
- ProMos Technologies Inc.
- Jon Allan Faue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable latch circuit inserted into write data path of an inte...
- Patent number 6,788,589
- Issue date Sep 7, 2004
- ProMos Technologies Inc.
- Jon Allan Faue
- G11 - INFORMATION STORAGE
Information Patent Grant
Pre-biased voltage level shifting circuit for integrated circuit de...
- Patent number 6,768,367
- Issue date Jul 27, 2004
- ProMos Technologies, Inc.
- Harold Brett Meadows
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated data input sorting and timing circuit for double data ra...
- Patent number 6,741,520
- Issue date May 25, 2004
- Mosel Vitelic, Inc.
- Jon Allan Faue
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-bank memory array architecture utilizing topologically non-un...
- Patent number 6,741,488
- Issue date May 25, 2004
- ProMos Technologies Inc.
- John Heightley
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated data input sorting and timing circuit for double data ra...
- Patent number 6,621,747
- Issue date Sep 16, 2003
- Mosel Vitelic, Inc.
- Jon Allan Faue
- G11 - INFORMATION STORAGE
Information Patent Grant
Arbitration method and circuit for control of integrated circuit do...
- Patent number 6,584,578
- Issue date Jun 24, 2003
- Mosel Vitelic, Inc.
- Jon Allan Faue
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated data input sorting and timing circuit for double data ra...
- Patent number 6,563,747
- Issue date May 13, 2003
- Mosel Vitelic, Inc.
- Jon Allan Faue
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for supporting sequential burst counts in double...
- Patent number 6,415,374
- Issue date Jul 2, 2002
- Mosel Vitelic, Inc.
- Jon Allan Faue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method of compensating for non-linear voltage-to-delay c...
- Patent number 6,359,487
- Issue date Mar 19, 2002
- Mosel Vitelic Inc
- John Heightley
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated clocking latency and multiplexer control technique for d...
- Patent number 6,337,830
- Issue date Jan 8, 2002
- Mosel Vitelic, Inc.
- Jon Allan Faue
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
LINEAR PROGRESSION DELAY REGISTER
- Publication number 20160065193
- Publication date Mar 3, 2016
- United Memories, Inc.
- Jon Allan Faue
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DUAL-COMPLEMENTARY INTEGRATING DUTY CYCLE DETECTOR WITH DEAD BAND N...
- Publication number 20150295564
- Publication date Oct 15, 2015
- United Memories, Inc.
- Oscar Frederick Jones
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SHIELDING OF DATALINES WITH PHYSICAL PLACEMENT BASED ON TIME STAGGE...
- Publication number 20090300255
- Publication date Dec 3, 2009
- PROMOS TECHNOLOGIES PTE.LTD.
- Jon Faue
- G11 - INFORMATION STORAGE
Information Patent Application
ASSYMETRIC DATA PATH POSITION AND DELAYS TECHNIQUE ENABLING HIGH SP...
- Publication number 20090231945
- Publication date Sep 17, 2009
- PROMOS TECHNOLOGIES PTE.LTD.
- Jon Allan Faue
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-BANK BLOCK ARCHITECTURE FOR INTEGRATED CIRCUIT MEMORY DEVICES...
- Publication number 20090231944
- Publication date Sep 17, 2009
- PROMOS TECHNOLOGIES PTE.LTD.
- Jon Allan Faue
- G11 - INFORMATION STORAGE
Information Patent Application
USING DIFFERENTIAL DATA STROBES IN NON-DIFFERENTIAL MODE TO ENHANCE...
- Publication number 20090190410
- Publication date Jul 30, 2009
- PROMOS TECHNOLOGIES PTE.LTD.
- Jon Faue
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
WIDE WINDOW CLOCK SCHEME FOR LOADING OUTPUT FIFO REGISTERS
- Publication number 20080291748
- Publication date Nov 27, 2008
- PROMOS TECHNOLOGIES PTE.LTD.
- Jon Allan Faue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WIDE WINDOW CLOCK SCHEME FOR LOADING OUTPUT FIFO REGISTERS
- Publication number 20080285371
- Publication date Nov 20, 2008
- PROMOS TECHNOLOGIES PTE.LTD.
- Jon Allan Faue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO-BIT PER I/O LINE WRITE DATA BUS FOR DDR1 AND DDR2 OPERATING MOD...
- Publication number 20080137462
- Publication date Jun 12, 2008
- ProMOS Technologies Inc.
- Jon Allan Faue
- G11 - INFORMATION STORAGE
Information Patent Application
Wide window clock scheme for loading output FIFO registers
- Publication number 20070091691
- Publication date Apr 26, 2007
- ProMOS Technologies PTE.LTD. Singapore
- Jon Allan Faue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Two-bit per I/O line write data bus for DDR1 and DDR2 operating mod...
- Publication number 20070008784
- Publication date Jan 11, 2007
- ProMOS Technologies Inc. Hsinchu
- Jon Allan Faue
- G11 - INFORMATION STORAGE
Information Patent Application
TRI-MODE CLOCK GENERATOR TO CONTROL MEMORY ARRAY ACCESS
- Publication number 20060245293
- Publication date Nov 2, 2006
- ProMOS Technologies Inc.
- Jon Allan Faue
- G11 - INFORMATION STORAGE
Information Patent Application
Efficient register for additive latency in DDR2 mode of operation
- Publication number 20060209618
- Publication date Sep 21, 2006
- ProMOS Technologies Inc.
- Jon Allan Faue
- G11 - INFORMATION STORAGE
Information Patent Application
Reduced device count level shifter with power savings
- Publication number 20060076975
- Publication date Apr 13, 2006
- ProMOS Technologies Inc.
- Jon Allan Faue
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Tri-mode clock generator to control memory array access
- Publication number 20060062064
- Publication date Mar 23, 2006
- Jon Allan Faue
- G11 - INFORMATION STORAGE
Information Patent Application
Limited output address register technique providing selectively var...
- Publication number 20060044925
- Publication date Mar 2, 2006
- Jon Allan Faue
- G11 - INFORMATION STORAGE
Information Patent Application
Dual equalization devices for long data line pairs
- Publication number 20060023529
- Publication date Feb 2, 2006
- Jon Allan Faue
- G11 - INFORMATION STORAGE
Information Patent Application
Low voltage differential amplifier circuit for wide voltage range o...
- Publication number 20050275461
- Publication date Dec 15, 2005
- John D. Heightley
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW VOLTAGE DIFFERENTIAL AMPLIFIER CIRCUIT AND A SAMPLED LOW POWER...
- Publication number 20050275462
- Publication date Dec 15, 2005
- John D. Heightley
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Data sorting in memories
- Publication number 20050195679
- Publication date Sep 8, 2005
- Jon Allan Faue
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated circuit memory architecture with selectively offset data...
- Publication number 20040172569
- Publication date Sep 2, 2004
- Jon Allan Faue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRE-BIASED VOLTAGE LEVEL SHIFTING CIRCUIT FOR INTEGRATED CIRCUIT DE...
- Publication number 20040145404
- Publication date Jul 29, 2004
- Harold Brett Meadows
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Limited variable width internal clock generation
- Publication number 20040140838
- Publication date Jul 22, 2004
- Jon Allan Faue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE LATCH CIRCUIT INSERTED INTO THE WRITE DATA PATH OF AN...
- Publication number 20040141373
- Publication date Jul 22, 2004
- Jon Allan Faue
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-BANK MEMORY ARRAY ARCHITECTURE UTILIZING TOPOLOGICALLY NON-UN...
- Publication number 20040095796
- Publication date May 20, 2004
- John Heightley
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated data input sorting and timing circuit for double data ra...
- Publication number 20030063514
- Publication date Apr 3, 2003
- Jon Allan Faue
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated data input sorting and timing circuit for double data ra...
- Publication number 20020149992
- Publication date Oct 17, 2002
- Jon Allan Faue
- G11 - INFORMATION STORAGE

Jon Allan Faue

Person

Patents Grantslast 30 patents

Linear progression delay register

Linear progression delay register

Dual-complementary integrating duty cycle detector with dead band n...

Shielding of datalines with physical placement based on time stagge...

Using differential data strobes in non-differential mode to enhance...

Asymetric data path position and delays technique enabling high spe...

Multi-bank block architecture for integrated circuit memory devices...

Wide window clock scheme for loading output FIFO registers

Two-bit per I/O line write data bus for DDR1 and DDR2 operating mod...

Tri-mode clock generator to control memory array access

Efficient register for additive latency in DDR2 mode of operation

Tri-mode clock generator to control memory array access

Dual equalization devices for long data line pairs

Low voltage differential amplifier circuit for wide voltage range o...

Low voltage differential amplifier circuit and a sampled low power...

Reduced device count level shifter with power savings

Limited output address register technique providing selectively var...

Integrated circuit memory architecture with selectively offset data...

Data sorting in memories

Limited variable width internal clock generation

Programmable latch circuit inserted into write data path of an inte...

Pre-biased voltage level shifting circuit for integrated circuit de...

Integrated data input sorting and timing circuit for double data ra...

Multi-bank memory array architecture utilizing topologically non-un...

Integrated data input sorting and timing circuit for double data ra...

Arbitration method and circuit for control of integrated circuit do...

Integrated data input sorting and timing circuit for double data ra...

System and method for supporting sequential burst counts in double...

System and method of compensating for non-linear voltage-to-delay c...

Integrated clocking latency and multiplexer control technique for d...

Patents Applicationslast 30 patents

LINEAR PROGRESSION DELAY REGISTER

DUAL-COMPLEMENTARY INTEGRATING DUTY CYCLE DETECTOR WITH DEAD BAND N...

SHIELDING OF DATALINES WITH PHYSICAL PLACEMENT BASED ON TIME STAGGE...

ASSYMETRIC DATA PATH POSITION AND DELAYS TECHNIQUE ENABLING HIGH SP...

MULTI-BANK BLOCK ARCHITECTURE FOR INTEGRATED CIRCUIT MEMORY DEVICES...

USING DIFFERENTIAL DATA STROBES IN NON-DIFFERENTIAL MODE TO ENHANCE...

WIDE WINDOW CLOCK SCHEME FOR LOADING OUTPUT FIFO REGISTERS

WIDE WINDOW CLOCK SCHEME FOR LOADING OUTPUT FIFO REGISTERS

TWO-BIT PER I/O LINE WRITE DATA BUS FOR DDR1 AND DDR2 OPERATING MOD...

Wide window clock scheme for loading output FIFO registers

Two-bit per I/O line write data bus for DDR1 and DDR2 operating mod...

TRI-MODE CLOCK GENERATOR TO CONTROL MEMORY ARRAY ACCESS

Efficient register for additive latency in DDR2 mode of operation

Reduced device count level shifter with power savings

Tri-mode clock generator to control memory array access

Limited output address register technique providing selectively var...

Dual equalization devices for long data line pairs

Low voltage differential amplifier circuit for wide voltage range o...

LOW VOLTAGE DIFFERENTIAL AMPLIFIER CIRCUIT AND A SAMPLED LOW POWER...

Data sorting in memories

Integrated circuit memory architecture with selectively offset data...

PRE-BIASED VOLTAGE LEVEL SHIFTING CIRCUIT FOR INTEGRATED CIRCUIT DE...

Limited variable width internal clock generation

PROGRAMMABLE LATCH CIRCUIT INSERTED INTO THE WRITE DATA PATH OF AN...

MULTI-BANK MEMORY ARRAY ARCHITECTURE UTILIZING TOPOLOGICALLY NON-UN...

Integrated data input sorting and timing circuit for double data ra...

Integrated data input sorting and timing circuit for double data ra...