Jonathan F. Churchill

Person

Reading, GB

People

Patents Grantslast 30 patents

Information Patent Grant
Power on reset circuits
- Patent number 7,126,391
- Issue date Oct 24, 2006
- Cypress Semiconductor Corporation
- Sean Smith
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Verification of integrated circuit designs using buffer control
- Patent number 6,981,238
- Issue date Dec 27, 2005
- Cypress Semiconductor Corporation
- Jonathan F. Churchill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual tristate path output buffer control
- Patent number 6,724,232
- Issue date Apr 20, 2004
- Cypress Semiconductor Corp.
- Jonathan F. Churchill
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dual tristate path output buffer control
- Patent number 6,538,485
- Issue date Mar 25, 2003
- Cypress Semiconductor Corp.
- Jonathan F. Churchill
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Wired address compare circuit and method
- Patent number 6,404,682
- Issue date Jun 11, 2002
- Cypress Semiconductor Corp.
- James W. Lutley
- G11 - INFORMATION STORAGE
Information Patent Grant
Wordline and pseudo read stress test for SRAM
- Patent number 6,392,941
- Issue date May 21, 2002
- Cypress Semiconductor Corp.
- Jonathan F. Churchill
- G11 - INFORMATION STORAGE
Information Patent Grant
Direct bit line-bit line defect detection test mode for SRAM
- Patent number 6,388,927
- Issue date May 14, 2002
- Cypress Semiconductor Corp.
- Jonathan F. Churchill
- G11 - INFORMATION STORAGE
Information Patent Grant
Wired address compare circuit and method
- Patent number 6,288,948
- Issue date Sep 11, 2001
- Cypress Semiconductor Corp.
- James W. Lutley
- G11 - INFORMATION STORAGE
Information Patent Grant
Scan path circuitry including a programmable delay circuit
- Patent number 6,286,118
- Issue date Sep 4, 2001
- Cypress Semiconductor Corporation
- Jonathan F. Churchill
- G01 - MEASURING TESTING
Information Patent Grant
Scan path circuitry for programming a variable clock pulse width
- Patent number 6,115,836
- Issue date Sep 5, 2000
- Cypress Semiconductor Corporation
- Jonathan F. Churchill
- G01 - MEASURING TESTING
Information Patent Grant
Test mode features for synchronous pipelined memories
- Patent number 6,006,347
- Issue date Dec 21, 1999
- Cypress Semiconductor Corporation
- Jonathan F. Churchill
- G11 - INFORMATION STORAGE
Information Patent Grant
Scan path circuitry including an output register having a flow thro...
- Patent number 5,953,285
- Issue date Sep 14, 1999
- Cypress Semiconductor Corp.
- Jonathan F. Churchill
- G11 - INFORMATION STORAGE
Information Patent Grant
Scan path circuitry including a programmable delay circuit
- Patent number 5,936,977
- Issue date Aug 10, 1999
- Cypress Semiconductor Corp.
- Jonathan F. Churchill
- G01 - MEASURING TESTING
Information Patent Grant
Dynamic voltage reference which compensates for process variations
- Patent number 5,907,255
- Issue date May 25, 1999
- Cypress Semiconductor
- Jonathan F. Churchill
- G05 - CONTROLLING REGULATING
Information Patent Grant
Method and circuit for preventing and/or inhibiting contention in a...
- Patent number 5,852,579
- Issue date Dec 22, 1998
- Cypress Semiconductor Corporation
- Mathew R. Arcoleo
- G11 - INFORMATION STORAGE
Information Patent Grant
Overvoltage tolerant intergrated circuit output buffer
- Patent number 5,570,043
- Issue date Oct 29, 1996
- Cypress Semiconductor Corporation
- Jonathan F. Churchill
- H03 - BASIC ELECTRONIC CIRCUITRY

Jonathan F. Churchill

Person

Patents Grantslast 30 patents

Power on reset circuits

Verification of integrated circuit designs using buffer control

Dual tristate path output buffer control

Dual tristate path output buffer control

Wired address compare circuit and method

Wordline and pseudo read stress test for SRAM

Direct bit line-bit line defect detection test mode for SRAM

Wired address compare circuit and method

Scan path circuitry including a programmable delay circuit

Scan path circuitry for programming a variable clock pulse width

Test mode features for synchronous pipelined memories

Scan path circuitry including an output register having a flow thro...

Scan path circuitry including a programmable delay circuit

Dynamic voltage reference which compensates for process variations

Method and circuit for preventing and/or inhibiting contention in a...

Overvoltage tolerant intergrated circuit output buffer